ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 21

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 15. Pin Function Descriptions
Pin No.
13, 12,
9 to 2
29 to 25,
18 to 14
62 to 58,
55 to 51
30
63
50
49
22
23
24
48
47
36
Mnemonic
Y9 to Y0
C9 to C0
S9 to S0
CLKIN_A
CLKIN_B
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
SFL
R
R
SET1
SET2
Input/
Output
I
I
I
I
I
I/O
I/O
I
I
I
I/O
I
I
V
DGND
DD_IO
V
C0
C1
C2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
DD
Y8
Y9
Description
10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 36 for input modes.
10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 36 for input modes.
10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 36 for input modes.
Pixel Clock Input for HD Only (74.25 MHz), ED
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
Subcarrier Frequency Lock (SFL) Input. The SFL input is used to drive the color subcarrier DDS
system, timing reset, or subcarrier reset.
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
AGND. For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
Figure 20. Pin Configuration
ADV7340/ADV7341
SET1
Rev. A | Page 21 of 108
(Not to Scale)
to AGND.
TOP VIEW
SET2
to AGND.
1
Only (27 MHz or 54 MHz), or SD Only (27 MHz).
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SFL
R
V
COMP1
DAC 1
DAC 2
DAC 3
V
AGND
DAC 4
DAC 5
DAC 6
R
COMP2
PV
EXT_LF1
REF
AA
SET1
SET2
DD
ADV7340/ADV7341
SET1
to