ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 70

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
Table 58. VSYNC Output Control
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
X
X
0
1
1
X
X
1
2
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV7340/ADV7341
support an Analog Devices proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To use this low power
mode, these DACs must be operating in full-drive mode (R
510 Ω, R
drive mode (R
be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10
The ADV7340/ADV7341 include an Analog Devices proprietary
cable detection feature. The cable detection feature is available
on DAC 1 and DAC 2, while operating in full-drive mode (R
= 510 Ω, R
is not available in low-drive mode (R
For a DAC to be monitored, the DAC must be powered up in
Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
X
= don’t care.
L
= 37.5 Ω). Low power mode is not available in low-
L1
= 37.5 Ω, assuming a connected cable). The feature
SET
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
X
X
0
0
0
1
1
= 4.12 kΩ, R
L
= 300 Ω). Low power mode can
ED/HD Sync
Output
Enable
(Subaddress
0x02, Bit 7)
0
0
1
1
1
1
1
, 1 2
SET1
= 4.12 kΩ, R
SD Sync Output
Enable (Subad-
dress 0x02, Bit 6)
0
1
X
X
X
X
X
L
= 300 Ω).
SET1
Rev. A | Page 70 of 108
SET1
=
Video Standard
X
Interlaced
X
All HD interlaced
standards
All ED/HD progressive
standards
All ED/HD standards
except 525p
525p
DAC 1 is monitored; that is, the luma or green output is
monitored.
Once per frame, the ADV7340/ADV7341 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down feature
can be enabled using Subaddress 0x10, Bit 4. This feature is
available only when the cable detection feature is enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is uncon-
nected, all three DACs power down. DAC 2 is not monitored
for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame when the
process is repeated.
Signal on S_VSYNC Pin
Three-state
Pipelined SD VSYNC/Field
Pipelined ED/HD VSYNC
or field signal
Pipelined field signal
based on the AV Code F bit
Pipelined VSYNC based
on the AV Code V bit
Pipelined ED/HD VSYNC
based on the vertical
counter
Pipelined ED/HD VSYNC
based on the vertical
counter
Duration
N/A
See SD Timing
As per VSYNC or
field signal timing
Field
Vertical blanking
interval
Aligned with
serration lines
Vertical blanking
interval