ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 55

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
1
2
3
4
5
FOR EXAMPLE, VCR OR CABLE.
F
SEQUENCE BIT
RESET ADV7340/ADV7341 DDS.
SELECTED BY SUBADDRESS 0x01, BIT 7.
F
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
SC
NO F
F
SC
RTC
SC
307
307
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7340/ADV7341 F
PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
RESET APPLIED
Figure 62. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits[2:1] = 11)
SC
RESET APPLIED
H/L TRANSITION
COMPOSITE
COUNT START
VIDEO
Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 01)
TIME SLOT 01
DISPLAY
DISPLAY
128
1
310
310
LOW
ADV7403
VIDEO
DECODER
13
LLC1
SUBCARRIER
14 BITS
PHASE
P[19:10]
SFL
14
0
313
313
4 BITS
RESERVED
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
Rev. A | Page 55 of 108
21
19
ADV7340/ADV7341
CLKIN_A
SFL
Y[9:0]/S[9:0]
SAMPLE
F
VALID
the incoming VSYNC signal. This control is available in all
slave-timing modes except slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7340/ADV7341 are able to accept input data that
contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and
HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame or on Line 6 to
Line 43 for the ITU-R BT.1358 (625p) standard. VBI data can
be present on Line 10 to Line 20 for NTSC and on Line 7 to
Line 22 for PAL.
SC
PLL INCREMENT
5
INVALID
SAMPLE
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
SC
DDS REGISTER IS
2
F
320
320
SC
8/LINE
LOCKED
CLOCK
SEQUENCE
F
SC
PHASE = FIELD 4 OR 8
PHASE = FIELD 1
0
BIT
3
F
SC
6768
5 BITS
RESERVED
RESET PULSE
RESERVED
RESET BIT
ADV7340/ADV7341
4