SAA7105E/V1/G-T NXP Semiconductors, SAA7105E/V1/G-T Datasheet - Page 41

• Manufacturer Part Number: SAA7105E/V1/G-T
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G-T

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,518

Philips Semiconductors
Table 69 Subaddress 84H
Table 70 Logic levels and function of PCLE
Table 71 Logic levels and function of PCLI
Table 72 Subaddress 85H
Table 73 Subaddresses 90H and 94H
2004 Mar 04
DCLK
PCLSY
IFRA
IFBP
PCLE
PCLI
EIDIV
FILI
XOFS
DATA BYTE
DATA BYTE
DATA BYTE
Digital video encoder
PCLE1
PCLI1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
LOGIC
LEVEL
PCLE0
LOGIC
LEVEL
PCLI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
set to logic 1 (default after reset is logic 0)
pixel clock generator runs free; default after reset
pixel clock generator gets synchronized with the vertical sync
input FIFO gets reset explicitly at falling edge
input FIFO gets reset every field; default after reset
input FIFO is active
input FIFO is bypassed; default after reset
controls the divider for the external pixel clock; see Table 70
controls the divider for the internal pixel clock; see Table 71
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2; default after reset
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
divider ratio for internal PIXCLK is 1
divider ratio for internal PIXCLK is 2; default after reset
divider ratio for internal PIXCLK is 4
not allowed
set to logic 0 if DVO compliant signals are applied; default after reset
set to logic 1 if non-DVO compliant signals are applied
threshold for FIFO internal transfers; nominal value is 8; default after reset
41
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7104E; SAA7105E
Product specification