AD9923BBCZRL Analog Devices Inc, AD9923BBCZRL Datasheet - Page 13

• Manufacturer Part Number: AD9923BBCZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

THEORY OF OPERATION
Figure 14 shows the typical system block diagram for the
AD9923 in master mode. The CCD output is processed by the
AD9923 AFE circuitry, which consists of a CDS, VGA, black level
clamp, and ADC. The digitized pixel information is sent to the
digital image processor chip, which performs the postprocessing
and compression. To operate the CCD, CCD timing parameters
are programmed into the AD9923 from the system microprocessor
through the 3-wire serial interface. The AD9923 generates the
CCD horizontal and vertical clocks and the internal AFE clocks
from the system master clock, CLI, which is provided by the
image processor or external crystal. External synchronization is
provided by a sync pulse from the microprocessor, which resets
internal counters and resyncs the VD and HD outputs.
Alternatively, the AD9923 can be operated in slave mode, in
which the VD and HD are provided externally from the image
processor. In this mode, the AD9923 timing is synchronized
with VD and HD.
The H-drivers for HL, H1 to H4, and RG are included in the
AD9923, allowing these clocks to be directly connected to the
CCD. An H-driver voltage, HVDD, of up to 3.3 V is supported.
An external V-driver is required for the vertical transfer clocks,
the sensor gate pulses, and the substrate clock.
The AD9923 also includes programmable MSHUT and
STROBE outputs, which can be used to trigger mechanical
shutter and strobe (flash) circuitry.
CLI
HD
VD
MAX VD LENGTH IS 4096 LINES
MAX HD LENGTH IS 8192 PIXELS
Figure 16. Maximum VD/HD Dimensions
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Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9923. Internal horizontal
and vertical clocking is controlled by these counters to specify
line and pixel locations. The maximum HD length is 8192 pixels
per line, and the maximum VD length is 4096 lines per field.
CCD
HL, H1 TO H4, RG, VSUB
MAXIMUM
COUNTER
DIMENSIONS
Figure 14. Typical System Block Diagram, Master Mode
V1 TO V13, SUBCK
13-BIT HORIZONTAL = 8192 PIXELS MAX
STROBE
MSHUT
Figure 15. Vertical and Horizontal Counters
CCDIN
12-BIT VERTICAL = 4096 LINES MAX
SYNC
AD9923
V-DRIVER
AFETG +
SERIAL
INTERFACE
HD, VD
DOUT
DCLK
CLI
μP
PROCESSING
DIGITAL
AD9923
IMAGE
ASIC