AD9923BBCZRL Analog Devices Inc, AD9923BBCZRL Datasheet - Page 14

• Manufacturer Part Number: AD9923BBCZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

AD9923
PRECISION TIMING
HIGH SPEED TIMING GENERATION
The AD9923 generates high speed timing signals using the
flexible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE. It
consists of reset gate RG, horizontal drivers H1 to H4 and HL,
and sample clocks SHP and SHD. A unique architecture makes
it routine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout and
the AFE-correlated double sampling.
The high speed timing of the AD9923 operates the same in
master and slave modes. For more information on
synchronization and pipeline delays, see the Power-Up and
Synchronization in Slave Mode section.
Timing Resolution
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. The frequency of this clock should match the CCD
pixel clock frequency. Figure 17 illustrates how the internal
timing core divides the master clock period into 48 steps, or
edge positions. Using a 36 MHz CLI frequency, the edge
resolution of the Precision Timing core is approximately 0.6 ns.
If a 1× system clock is not available, a 2× reference clock can be
used by programming the CLIDIVIDE register (Address 0x30).
The AD9923 then internally divides the CLI frequency by 2.
The AD9923 includes a master clock output, CLO, which is the
inverse of CLI. This output is intended to be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins
to generate the master clock for the AD9923. For more
information on using a crystal, see Figure 79.
High Speed Clock Programmability
Figure 18 shows how the high speed clocks, RG, HL, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The horizontal clocks, HL, H1, and H3, have program-
mable rising and falling edges and polarity control. The H2 and
H4 clocks are inverses of the H1 and H3 clocks, respectively.
Table 9 summarizes the high speed timing registers and their
parameters. Figure 19 shows the typical 2-phase, H-clock
operation, in which H3 and H4 are programmed for the same
edge location as H1 and H2.
Table 9. Timing Core Register Parameters for HL, H1 to H4, RG, SHP/SHD
Parameter
Polarity
Positive Edge
Negative Edge
Sampling
Location
Drive Strength
Length
(Bits)
1
6
6
6
3
Range
High/low
0 to 47 edge location
0 to 47 edge location
0 to 47 edge location
0 to 7 current steps
Description
Polarity control for HL, H1, H3, and RG (0 = no inversion, 1 = inversion)
Positive edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)
Negative edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)
Sampling location for internal SHP and SHD signals
Drive current for HL, H1 to H4, and RG outputs (4.1 mA per step)
Rev. 0 | Page 14 of 88
The edge location registers are six bits wide, but there are only
48 valid edge locations available. Therefore, the register values
are mapped into four quadrants, each of which contains 12 edge
locations. Table 10 shows the correct register values for the
corresponding edge locations. Figure 20 shows the default
timing locations for high speed clock signals.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9923
features on-chip output drivers for the RG and H1 to H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG current can be adjusted for optimum
rise/fall times in a particular load by using the H1 to H4, HL,
and RGDRV registers (Address 0x36). The 3-bit drive setting
for each output can be adjusted in 4.1 mA increments, with the
minimum setting of 0 equal to 0 mA or three-state, and the
maximum setting of 7 equal to 30.1 mA.
As shown in Figure 18, Figure 19, and Figure 20, the H2 and H4
outputs are inverses of H1 and H3 outputs, respectively. The
H1/H2 crossover voltage is approximately 50% of the output
swing. The crossover voltage is not programmable.
Digital Data Outputs
The AD9923 data output and DCLK phase are programmable
using the DOUTPHASE register (Address 0x38, Bits[5:0]). Any
edge from 0 to 47 can be programmed, as shown in Figure 21.
Normally, the DOUT and DCLK signals track in phase, based
on the DOUTPHASE register contents. The DCLK output
phase can also be held fixed with respect to the data outputs by
setting the DCLKMODE register to high (Address 0x38, Bit[8]).
In this mode, the DCLK output remains at a fixed phase equal
to a delayed version of CLI, and the data output phase remains
programmable. For more detail, see the Analog Front End
Description/Operation section.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called t
four values between 0 ns and 12 ns, using the DOUTDELAY
register (Address 0x38, Bits[10:9]). The default value is 8 ns.
The pipeline delay through the AD9923 is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay before the data is available.
OD
. This delay can be programmed to