STAC9766XXTAEC1X IDT, Integrated Device Technology Inc, STAC9766XXTAEC1X Datasheet - Page 78

• Manufacturer Part Number: STAC9766XXTAEC1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9766XXTAEC1X

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135/4.75V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
8.4.11.
Bit(s) Reset Value
14:12
Bit(s) Reset Value
10:3
15:8
6:0
15
11
2
1
0
7
EAPD
D15
D7
EAPD Access Register (74h)
Default: 0800h
0
0
1
0
0
0
0
0
0
0
D14
D6
RESERVED Bit not used, should read back 0
RESERVED Bit not used, should read back 0
EAPD_OEN
GPIOSLT12
RESERVED Reserved
RESERVED Reserved
INT_APOP
GPIOACC
INTDIS
Name
EAPD
Name
RESERVED
RESERVED
D13
D5
EAPD data Enable
EAPD data output on EAPD when bit D11 = 1
EAPD data input from pin when bit D11 = 0
EAPD Pin Enable
0 = EAPD configured as input pin
1 = EAPD configured as output pin
Interrupt disable option.
Interrupts cleared by writing a 1 to I4 (Reg24h:D15)
0 = will clear both SENSE and GPIO interrupts
1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in
Reg54h.
GPIO ACCESS
0 = ACLINK access from GPIO Pads
1 = ACLINK access from GPIO Register 54h
0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot12
data will be 0h.
1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs
Reg54h will not be updated.
This can only be used if a modem CODEC is not present in the system and using
Slot12.
0 = Anti Pop Enabled
1 = Anti Pop Disabled
The STAC9766/9767 includes an internal power supply anti-pop circuit that
prevents audible clicks and pops from being heard when the CODEC is powered
on and off. This function is accomplished by delaying the charge/discharge of the
VREF capacitor (Pin 27). C
3 seconds, which will allow the power supplies to stabilize before the CODEC
outputs are enabled. The delay will be extended to 30 seconds if a C
10 F is used. The CODEC outputs are also kept stable for the same amount of
time at power-off to allow the system to be gracefully turned off. The INT_APOP bit
allows this delay circuit to be bypassed for rapid production testing. Any external
component anti-pop circuit is unaffected by the internal circuit.
D12
78
D4
EAPD_OEN
VREF
D11
D3
value of 1 F will cause a turn-on delay of roughly
Description
Description
INTDIS
STAC9766/9767
D10
D2
RESERVED
GPIOACC
D9
D1
VREF
GPIOSLT12
PC AUDIO
V 7.4 12/06
value of
D8
D0