USB3300-EZK-TR Standard Microsystems (SMSC), USB3300-EZK-TR Datasheet - Page 7

• Manufacturer Part Number: USB3300-EZK-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3300-EZK-TR

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: QFN
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
SMSC USB3300
PIN
10
12
13
14
15
16
11
5
6
7
8
9
EXTVBUS
CLKOUT
VDD3.3
VDD1.8
VDD3.3
RESET
NAME
NXT
STP
DIR
DM
DP
ID
Table 1 USB3300 Pin Definitions (continued)
Input, CMOS
Input, CMOS
DIRECTION,
Output,
Output,
Output,
Analog
Analog
Analog
CMOS
CMOS
CMOS
CMOS
Power
Power
Power
TYPE
Input,
Input,
I/O,
I/O,
PRODUCT PREVIEW
ACTIVE
LEVEL
High
High
High
High
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7
DESCRIPTION
ID pin of the USB cable. For non-OTG applications
this pin can be floated. For an A-Device ID = 0. For
a B-Device ID = 1.
3.3V Supply. A 0.1uF bypass capacitor should be
connected between this pin and the ground plane on
the PCB.
D+ pin of the USB cable.
D- pin of the USB cable.
Optional active high transceiver reset. This is the
same as a write to the ULPI Reset, address 04h, bit
5. This does not reset the ULPI register set. This pin
includes an integrated pull-down resistor to ground.
If not used, this pin can be floated or connected to
ground (recommended).
External Vbus Detect. Connect to fault output of an
external USB power switch or an external Vbus Valid
comparator. This pin has a pull down resistor to
prevent it from floating when the ULPI bit
UseExternalVbusIndicator is set to 0.
The PHY asserts NXT to throttle the data. When the
Link is sending data to the PHY, NXT indicates when
the current byte has been accepted by the PHY. The
Link places the next byte on the data bus in the
following clock cycle.
Controls the direction of the data bus. When the
PHY has data to transfer to the Link, it drives DIR
high to take ownership of the bus. When the PHY
has no data to transfer it drives DIR low and
monitors the bus for commands from the Link. The
PHY will pull DIR high whenever the interface cannot
accept data from the Link, such as during PLL start-
up.
The Link asserts STP for one clock cycle to stop the
data stream currently on the bus. If the Link is
sending data to the PHY, STP indicates the last byte
of data was on the bus in the previous cycle.
60MHz reference clock output. All ULPI signals are
driven synchronous to the rising edge of this clock.
1.8V for digital circuitry on chip. Supplied by On-Chip
Regulator when REG_EN is active. Place a 0.1uF
capacitor near this pin and connect the capacitor
from this pin to ground. Connect pin 15 to pin 26.
A 0.1uF bypass capacitor should be connected
between this pin and the ground plane on the PCB.
Revision 1.08 (11-07-07)