XC3S250E-4TQG144I Xilinx Inc, XC3S250E-4TQG144I Datasheet - Page 157
![FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S250E-4TQG144I
Manufacturer Part Number
XC3S250E-4TQG144I
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4TQG144I
Package
144TQFP
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
108
Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Total Ram Bits
221184
Number Of I /o
108
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
813-1009 - MODULE USB-TO-FPGA TOOL W/MANUAL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 119: Configuration Timing Requirements for Attached SPI Serial Flash
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
Symbol
CCS
DSU
DH
V
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Description
www.xilinx.com
T
T
T
CCS
V
f
DSU
DC and Switching Characteristics
C
T
≤
≥
DH
T
Requirement
≤
≤
------------------------------ -
T
MCCLn
T
≤
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
–
(
T
–
–
DCC
T
)
T
CCO
CCO
Units
MHz
ns
ns
ns
ns
157
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