AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 13

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal
REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 13 to Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 13 is a direct result of sampling the
fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which
effectively lowers the noise floor.
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CENTER 39.1MHz
CENTER 39.1MHz
CENTER 39.1MHz
Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
Figure 12. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiply Bypassed
300 MHz REFCLK with REFCLK Multiply Bypassed
30 MHz REFCLK with REFCLK Multiply = 10×
100kHz/
100kHz/
5kHz/
SPAN 50kHz
SPAN 1MHz
SPAN 1MHz
Rev. D | Page 13 of 52
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CENTER 39.1MHz
CENTER 39.1MHz
CENTER 39.1MHz
Figure 13. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiply Bypassed
30 MHz REFCLK with REFCLK Multiply = 10×
10 MHz REFCLK with REFCLK Multiply = 10×
5kHz/
5kHz/
5kHz/
SPAN 50kHz
SPAN 50kHz
SPAN 50kHz
AD9854