AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 23

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

Figure 41 shows that premature toggling causes the ramp to
immediately reverse itself and proceed at the same rate and
resolution until the original frequency is reached.
The control register contains a triangle bit at Parallel Register
Address 1F hex. Setting this bit high in Mode 010 causes an
automatic ramp-up and ramp-down between F1 and F2 to
occur without toggling Pin 29, as shown in Figure 40. The logic
state of Pin 29 has no effect once the triangle bit is set high. This
function uses the ramp rate clock time period and the delta
frequency word step size to form a continuously sweeping linear
ramp from F1 to F2 and back to F1 with equal dwell times at
every frequency. Use this function to automatically sweep
between any two frequencies from dc to Nyquist.
In the ramped FSK mode with the triangle bit set high, an
automatic frequency sweep begins at either F1 or F2, according
to the logic level on Pin 29 (FSK input pin) when the triangle
I/O UD CLK
FSK DATA
MODE
TW1
TW2
000 (DEFAULT)
F2
F1
I/O UD CLK
TRIANGLE
FSK DATA
0
0
0
MODE
TW1
TW2
BIT
Figure 40. Effect of Triangle Bit in Ramped FSK Mode
Figure 41. Effect of Premature Ramped FSK Data
F2
F1
0
Rev. D | Page 23 of 52
010 (RAMPED FSK)
010 (RAMPED FSK)
F1
F2
bit’s rising edge occurs (Figure 42). If the FSK data bit is high
instead of low, F2, rather than F1, is chosen as the start frequency.
Additional flexibility in the ramped FSK mode is provided in
the ability to respond to changes in the 48-bit delta frequency
word and/or the 20-bit ramp rate counter on the fly during the
ramping from F1 to F2 or vice versa. To create these nonlinear
frequency changes, it is necessary to combine several linear
ramps with different slopes in a piecewise fashion. This is done
by programming and executing a linear ramp at some rate or
slope and then altering the slope (by changing the ramp rate
clock or delta frequency word or both). Changes in slope are
made as often as needed to form the desired nonlinear
frequency sweep response before the destination frequency is
reached. These piecewise changes can be precisely timed using
the 32-bit internal update clock (see the Internal and External
Update Clock section).
F2
F1
AD9854