AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 27

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

The 32-bit automatic I/O update counter can be used to
construct complex chirp or ramped FSK sequences. Because
this internal counter is synchronized with the AD9854 system
clock, precisely timed program changes are possible. For such
changes, the user need only reprogram the desired registers
before the automatic I/O update clock is generated.
In chirp mode, the destination frequency is not directly specified.
If the user fails to control the chirp, the DDS automatically confines
itself to the frequency range between dc and Nyquist. Unless
terminated by the user, the chirp continues until power is removed.
When the chirp destination frequency is reached, the user can
choose any of the following actions:
•
•
•
•
•
Stop at the destination frequency by using the HOLD pin
or by loading all zeros into the delta frequency word
registers of the frequency accumulator (ACC1).
Use the hold function to stop the chirp, and then ramp
down the output amplitude by using the digital multiplier
stages and the shaped keying pin, Pin 30, or by using the
program register control (Addresses 21 to 24 hex).
Abruptly end the transmission with the CLR ACC2 bit.
Continue chirp by reversing direction and returning to
the previous, or another, destination frequency in a linear
or user directed manner. If this involves reducing the
frequency, a negative 48-bit delta frequency word (the
MSB is set to 1) must be loaded into Register 10 hex to
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
Continue chirp by immediately returning to the beginning
frequency (F1) in a saw-toothed fashion and then repeating
PHASE ADJUST 1
PHASE ADJUST 2
BPSK DATA
I/O UD CLK
MODE
FTW1
000 (DEFAULT)
360
0
0
Figure 48. BPSK Mode
Rev. D | Page 27 of 52
BPSK (Mode 100)
Binary, biphase, or bipolar-phase shift keying is a means to
rapidly select between two preprogrammed 14-bit output phase
offsets that equally affect both the I and Q outputs of the
AD9854. The logic state of Pin 29, the BPSK pin, controls the
selection of Phase Adjust Register 1 or 2. When low, Pin 29
selects Phase Adjust Register 1; when high, it selects Phase
Adjust Register 2. Table 7 illustrates phase changes made
to four cycles of an output carrier.
Basic BPSK Programming Steps
1.
2.
3.
4.
Note that for higher order PSK modulation, the user can select
the single-tone mode and program Phase Adjust Register 1
using the serial or high speed parallel programming bus.
100 (BPSK)
270°
the previous chirp process using the CLR ACC1 control
bit. An automatic, repeating chirp can be set up by using
the 32-bit update clock to issue the CLR ACC1 command
at precise time intervals. Adjusting the timing intervals or
changing the delta frequency word changes the chirp
range. It is incumbent upon the user to balance the chirp
duration and frequency resolution to achieve the proper
frequency range.
Program a carrier frequency into Frequency Tuning Word 1.
Program the appropriate 14-bit phase words in Phase
Adjust Register 1 and Phase Adjust Register 2.
Attach the BPSK data source to Pin 29.
Activate the I/O update clock when ready.
90°
F1
AD9854