PF38F1030W0YCQEA Micron Technology Inc, PF38F1030W0YCQEA Datasheet - Page 37
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PF38F1030W0YCQEA
Manufacturer Part Number
PF38F1030W0YCQEA
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F1030W0YCQEA.pdf
(102 pages)
Specifications of PF38F1030W0YCQEA
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Numonyx™ Wireless Flash Memory (W18)
Table 15: AC Write Characteristics — 90 nm (Sheet 2 of 2)
Table 16: AC Write Characteristics — 130 nm (Sheet 1 of 2)
November 2007
Order Number: 290701-18
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
W13
W14
W16
W18
W19
W20
W21
W22
W27
W28
W10
W11
W12
#
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
Write timing characteristics during erase suspend are the same as during write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
(whichever occurs first). Hence, t
Write pulse width high (t
(whichever is last). Hence, t
System designers should take this into account and may insert a software No-Op instruction to delay the first read after
issuing a command.
For commands other than resume commands.
V
Applicable during asynchronous reads following a write.
t
refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs first).
The specifications t
WHCH/L
PP
t
t
BHWH
WHGL
should be held at V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Sym
OR t
WHEH
DVWH
WHDX
WHAX
WHWL
WHQV
WHAV
WHCV
WHVH
WLWH
AVWH
VPWH
VHWL
CHWL
WHEL
WHVL
PHWL
ELWL
(t
(t
t
t
BHEH
EHGL
Sym
WHVH
QVVL
QVBL
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
EHWH
DVEH
PHEL
AVEH
EHDX
EHAX
VPEH
ELEH
EHEL
)
)
must be met when transitioning from a write cycle to a synchronous burst read. t
)
)
)
)
)
)
)
)
)
VHWL
)
WP# Setup to WE# (CE#) High
Write Recovery before Read
WE# High to Valid Data
WE# High to Address Valid
WE# High to CLK Valid
WE# High to ADV# High
ADV# High to WE# Low
CLK to WE# Low
WE# High to CE# Low
WE# High to ADV# Low
PP1
WLWH
and t
WHWL
RST# High Recovery to WE# (CE#) Low
CE# (WE#) Setup to WE# (CE#) Low
WE# (CE#) Write Pulse Width Low
Data Setup to WE# (CE#) High
Address Setup to WE# (CE#) High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
VPP Setup to WE# (CE#) High
VPP Hold from Valid SRD
WP# Hold from Valid SRD
or V
WLWH
or t
CHWL
or t
PP2
ELEH
WLWH
= t
EHEL
until block erase or program success is determined.
can be ignored if there is no clock toggling during the write bus cycle.
Parameter
EHEL
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
= t
Parameter
= t
ELEH
WHEL
= t
(1,2)
WLEH
= t
(1,2)
EHWL
= t
.
ELWH
.
t
AVQV
Min
200
12
12
0
0
0
0
Min
150
200
1.7 V – 1.95 V
1.7 V – 2.24 V
40
40
40
20
+20
0
0
0
0
0
0
V
V
CCQ
CCQ
-60
=
=
Max
Max
<21
<21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WHCH/L
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
and t
ns
ns
WHVH
Datasheet
Notes
5,6,7
Notes
3,6,10
3,9,10
3,8
3,8
3,10
3,10
3
4
3
11
11
both
3
37
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