MT48LC16M16A2P-75:D Micron Technology Inc, MT48LC16M16A2P-75:D Datasheet - Page 81
![IC, SDRAM, 256MBIT, 133MHZ, TSOP-54](/photos/19/4/190474/4467789_sml.jpg)
MT48LC16M16A2P-75:D
Manufacturer Part Number
MT48LC16M16A2P-75:D
Description
IC, SDRAM, 256MBIT, 133MHZ, TSOP-54
Manufacturer
Micron Technology Inc
Type
SDRAMr
Series
-r
Specifications of MT48LC16M16A2P-75:D
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Type
DRAM - Sychronous
Memory Configuration
16 X 16
Access Time
5.4ns
Page Size
256Mbit
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Format - Memory
RAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP (0.400", 10.16mm Width)
Lead Free Status / RoHS Status
Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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AUTO REFRESH Operation
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
The AUTO REFRESH command is used during normal operation of the device to refresh
the contents of the array. This command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be precharged prior to issuing an AUTO
REFRESH command. The AUTO REFRESH command should not be issued until the min-
imum
internal refresh controller. This makes the address bits “Don’t Care” during an AUTO
REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-
cutable command until
NOP commands must be issued on each positive edge of the clock. The SDRAM re-
quires that every row be refreshed each
REFRESH command—calculated by dividing the refresh period (
rows to be refreshed—meets the timing requirement and ensures that each row is re-
freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be em-
ployed after every
the number of rows to be refreshed at the minimum cycle rate (
t
RP is met following the PRECHARGE command. Addressing is generated by the
t
REF period by issuing consecutive AUTO REFRESH commands for
t
RFC has been met. During
81
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
REF period. Providing a distributed AUTO
256Mb: x4, x8, x16 SDRAM
t
RFC time, COMMAND INHIBIT or
AUTO REFRESH Operation
© 1999 Micron Technology, Inc. All rights reserved.
t
RFC).
t
REF) by the number of