MT48LC16M16A2P-75:D Micron Technology Inc, MT48LC16M16A2P-75:D Datasheet - Page 85
![IC, SDRAM, 256MBIT, 133MHZ, TSOP-54](/photos/19/4/190474/4467789_sml.jpg)
MT48LC16M16A2P-75:D
Manufacturer Part Number
MT48LC16M16A2P-75:D
Description
IC, SDRAM, 256MBIT, 133MHZ, TSOP-54
Manufacturer
Micron Technology Inc
Type
SDRAMr
Series
-r
Specifications of MT48LC16M16A2P-75:D
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Type
DRAM - Sychronous
Memory Configuration
16 X 16
Access Time
5.4ns
Page Size
256Mbit
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Format - Memory
RAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP (0.400", 10.16mm Width)
Lead Free Status / RoHS Status
Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC16M16A2P-75:D
Manufacturer:
SAMTEC
Quantity:
1 200
Company:
Part Number:
MT48LC16M16A2P-75:D
Manufacturer:
MICRON
Quantity:
5 520
Company:
Part Number:
MT48LC16M16A2P-75:D
Manufacturer:
MICRON
Quantity:
6 000
Company:
Part Number:
MT48LC16M16A2P-75:D
Manufacturer:
MICRON42
Quantity:
175
Part Number:
MT48LC16M16A2P-75:D
Manufacturer:
MICRON
Quantity:
20 000
Power-Down
Figure 53: Power-Down Mode
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
Precharge all
active banks
DQM
CKE
CLK
A10
DQ
High-Z
t CMS
t CKS
PRECHARGE
t AS
Single bank
All banks
Bank(s)
T0
t CMH
t CKH
t AH
Note:
Two clock cycles
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is
a row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting
All banks idle, enter
power-down mode
t CK
1. Violating refresh requirements during power-down may result in a loss of data.
T1
NOP
t CL
t CKS
T2
NOP
t CH
Input buffers gated off
while in power-down mode
85
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
(
(
)
(
(
(
(
(
(
)
)
)
)
(
)
(
)
(
)
)
(
(
Exit power-down mode
(
)
)
)
)
)
(
)
(
Micron Technology, Inc. reserves the right to change products or specifications without notice.
)
)
t
CKS).
256Mb: x4, x8, x16 SDRAM
t CKS
Tn + 1
NOP
All banks idle
© 1999 Micron Technology, Inc. All rights reserved.
Tn + 2
Power-Down
ACTIVE
Row
Bank
Row
Don’t Care