MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 55

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Configuration Tables in Multiplexed Address Mode
Table 22:
REFRESH Command in Multiplexed Address Mode
Figure 35:
PDF: 09005aef815b2df8/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN
COMMAND
Valid frequency range
ADDRESS
BANK
CK#
CK
Parameter
t
t
t
WL
Bank n
RC
RL
AC
T0
Ax
1
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Notes 1–2 apply to the entire table
BURST REFRESH Operation with Multiplexed Addressing
Notes:
Notes:
NOP
T1
Ay
In multiplexed address mode, the read and write latencies are increased by one clock
cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed
address mode.
1.
2. Minimum operating frequency for -18 is 370 MHz.
3. BL = 8 is not available.
4. The minimum
Similar to other commands when in multiplexed address mode, AREF is executed on the
rising clock edge following the one on which the command is issued. However, since
only the bank address is required for AREF, the next command can be applied on the
following clock. The operation of the AREF command and any other command is repre-
sented in Figure 35 on page 58.
1. Any command.
2. Bank n is chosen so that
266–175
Bank 0
AREF
T2
t
the same bank. In this instance the minimum
RC < 20ns in any configuration is only available with -25E and -18 speed grades.
1
4
5
6
3
Bank 1
AREF
T3
t
RC is typically 3 cycles, except in the case of a WRITE followed by a READ to
400–175
288Mb: x18 2.5V V
Bank 2
AREF
T4
2
6
7
8
t
RC is met.
Bank 3
T5
AREF
58
Configuration
533–175
10
3
8
9
Bank 4
AREF
T6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
EXT
t
RC is 4 cycles.
Bank 5
, 1.8V V
T7
AREF
200–175
4
3, 4
3
4
5
Bank 6
T8
AREF
DD
, HSTL, SIO, RLDRAM II
©2003Micron Technology, Inc. All rights reserved.
Bank 7
T9
AREF
333–175
5
5
6
7
T10
Bank n
AC
Ax
Operations
1
DON’T CARE
Units
T11
MHz
t
t
t
Ay
CK
CK
CK