MT47H128M8HQ-3 L:E TR Micron Technology Inc, MT47H128M8HQ-3 L:E TR Datasheet - Page 80

• Manufacturer Part Number: MT47H128M8HQ-3 L:E TR
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:E TR

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Write Recovery
Power-Down Mode
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 77).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 113).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 34 (page 77).
PD mode enables the user to determine the active power-down mode, which deter-
mines performance versus power savings. PD mode bit M12 does not apply to pre-
charge PD mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between Idd3P normal and Idd3P low-
power mode is defined in the DDR2 Idd Specifications and Conditions table.
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
80
t
CK (ns). Reserved states should not be used as an un-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
© 2004 Micron Technology, Inc. All rights reserved.
t
WR (in