K4H561638F-ULB3 Samsung Semiconductor, K4H561638F-ULB3 Datasheet - Page 7

• Manufacturer Part Number: K4H561638F-ULB3
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H561638F-ULB3

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 200mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

DDR SDRAM 256Mb F-die (x8, x16) Pb-Free
Input/Output Function Description
RAS, CAS, WE
BA0, BA1
SYMBOL
L(U)DQS
A [0 : 12]
L(U)DM
CK, CK
VDDQ
VSSQ
VREF
CKE
VDD
VSS
DQ
CS
NC
Supply
Supply
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
-
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-
ing power-down and self refresh modes, providing low standby power. CKE will recognize an
LVCMOS LOW level prior to VREF being stable on power-up.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on
DQ8~DQ15. DM may be driven high, low, or floating during READs.
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V.
DQ Ground.
Power Supply : +2.5V ± 0.2V (device specific).
Ground.
SSTL_2 reference voltage.
DESCRIPTION
Rev. 1.2 October, 2004
DDR SDRAM