M45PE40-VMP6G Micron Technology Inc, M45PE40-VMP6G Datasheet - Page 29
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M45PE40-VMP6G
Manufacturer Part Number
M45PE40-VMP6G
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M45PE40-VMP6G.pdf
(49 pages)
Specifications of M45PE40-VMP6G
Cell Type
NOR
Density
4Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
VFQFPN EP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
8mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M45PE40-VMP6G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M45PE40-VMP6G
Manufacturer:
MICRON
Quantity:
20 000
M45PE40
6.10
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is t
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a sector that contains a page that is hardware
protected is not executed.
Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Sector erase (SE) instruction sequence
1. Address bits A23 to A19 are don’t care.
S
C
D
Table
2) is a valid address for the sector erase (SE) instruction. Chip Select (S)
0
1
2
Instruction
3
4
Figure
5
6
7
15.
MSB
23 22
8
9
24-bit address
2
29 30 31
1
0
AI03751D
SE
Instructions
) is
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