MT45W4MW16PCGA-70 L WT Micron Technology Inc, MT45W4MW16PCGA-70 L WT Datasheet - Page 2

• Manufacturer Part Number: MT45W4MW16PCGA-70 L WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16PCGA-70 L WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

General Description
Figure 2:
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
WE#
OE#
UB#
CE#
ZZ#
LB#
Functional Block Diagram – 4 Meg x 16
A[21:0]
Notes:
Control
logic
1. Partial-array refresh (PAR) enables the system to limit refresh to only that part of the
2. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh
3. Deep power-down (DPD) enables the system to halt the REFRESH operation alto-
Micron
oped for low-power, portable applications. The MT45W4MW16PCGA is a 64Mb DRAM
core device, organized as 4 Meg x 16 bits. This device includes an industry-standard
asynchronous memory interface found on other low-power SRAM or PSRAM offerings.
For seamless operation on an asynchronous memory bus, CellularRAM products incor-
porate a transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
A user-accessible configuration register (CR) defines how the CellularRAM device
performs on-chip refresh and whether page mode read accesses are permitted. This
register is automatically loaded with a default setting during power-up and can be
updated at any time during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.0
feature set established by the CellularRAM Workgroup. The device also includes support
for a device ID register.
1. Functional block diagrams illustrate simplified device operation. For detailed information,
DRAM array that contains essential data.
rate to match the device temperature—the refresh rate decreases at lower tempera-
tures to minimize current consumption during standby.
gether when no vital information is stored in the device.
see ball descriptions in Table 1 on page 3, bus operations in Table 2 on page 3, and timing
diagrams starting on page 19.
®
CellularRAM™ products are high-speed CMOS PSRAM memory devices devel-
Device ID register
Address decode
Configuration
register (CR)
(DIDR)
logic
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
2
4,096K x 16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
memory
DRAM
array
Output
buffers
Input/
MUX
and
General Description
©2005 Micron Technology, Inc. All rights reserved.
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