MT45W4MW16PCGA-70 L WT Micron Technology Inc, MT45W4MW16PCGA-70 L WT Datasheet - Page 8

• Manufacturer Part Number: MT45W4MW16PCGA-70 L WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16PCGA-70 L WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Low-Power Operation
Standby Mode Operation
Temperature-Compensated Refresh (TCR)
Partial-Array Refresh (PAR)
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# and ZZ# are
HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation, or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
This CellularRAM device includes an on-chip temperature sensor that automatically
adjusts the refresh rate according to the operating temperature. The device continually
adjusts the refresh rate to match that temperature.
PAR restricts REFRESH operation to a portion of the total memory array. This feature
enables the system to reduce refresh current by refreshing only that part of the memory
array that is absolutely necessary. The refresh options are full array, one-half array, one-
quarter array, one-eighth array, or none of the array. Data stored in addresses not
receiving refresh will become corrupted. The mapping of these partitions can start at
either the beginning or the end of the address map (see Table 3 on page 10).
READ and WRITE operations are ignored during PAR operation. The device only enters
PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated
by bringing ZZ# LOW for longer than 10µs. Returning ZZ# HIGH will cause an exit from
PAR and the entire array will be immediately available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software access sequence (see “Software
Access to the Configuration Register” on page 12). PAR is enabled immediately upon
setting CR[4] to “1” using this method. However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up (see Figure 8 on page 9).
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2005 Micron Technology, Inc. All rights reserved.