MT45W2MW16BGB-701 IT Micron Technology Inc, MT45W2MW16BGB-701 IT Datasheet - Page 31

• Manufacturer Part Number: MT45W2MW16BGB-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Refresh Configuration Register
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
Figure 24:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
RCR[19]
1
0
Refresh Configuration Register Mapping
Register Select
Select RCR
Select BCR
RCR[7]
0
1
Must be set to “0”
Page mode disabled (default)
Page mode enable
Page Mode Enable/Disable
Reserved
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce
current consumption during standby mode. Page mode control is also embedded into
the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is
set to 0010h.
The RCR is accessed using CRE and A[19] LOW or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 20.)
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature enables the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start either at the beginning or the end of the address map (see Table 6 on
page 32).
20
A20
Register
Select
All must be set to “0”
19
A19
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Reserved
18–8
A[18:8]
Page
7
A7
Setting is ignored
(default 00b)
Ignored
6
A6
31
5
A5
RCR[4]
DPD
0
1
4
A4
Must be set to “0”
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved
Deep Power-Down
DPD enable
DPD disable (default)
3
A3
RCR[2]
0
0
0
0
1
1
1
1
2
A2
RCR[1]
1
1
1
0
0
0
0
1
PAR
Configuration Registers
1
A1
RCR[0]
0
1
0
1
1
0
0
1
©2007 Micron Technology, Inc. All rights reserved.
Refresh Coverage
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/8 array
Top 1/4 array
Full array (default)
Bottom 1/2 array
A0
0
Address Bus