MT45W2MW16BGB-701 IT Micron Technology Inc, MT45W2MW16BGB-701 IT Datasheet - Page 9

• Manufacturer Part Number: MT45W2MW16BGB-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 3:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
Mode
Asynchronous
READ
Asynchronous
WRITE
Standby
No operation
Initial burst
READ
Initial burst
WRITE
Burst continue
Burst suspend
Configuration
register WRITE
Configuration
register READ
DPD
Bus Operations: Burst Mode
Notes:
power-down
Standby
Power
Active
Active
Active
Active
Active
Active
Active
Active
Deep
Idle
1. CLK must be static (HIGH or LOW) during asynchronous READ and asynchronous WRITE
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
6. V
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. This device supports CRE-controlled configuration register READs. This feature is not an
modes and to achieve standby power during standby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are
affected.
isolated from any external influence.
official CellularRAM 1.0 feature.
IN
CLK
= V
X
L
L
L
L
L
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
CC
1
Q or 0V; all device balls must be static (unswitched) to achieve standby current.
ADV#
X
X
H
X
X
L
L
L
L
L
L
CE#
H
H
L
L
L
L
L
L
L
L
L
OE#
9
X
X
X
X
H
X
H
H
H
X
L
WE#
H
X
X
H
X
X
H
X
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CRE
X
H
H
X
L
L
L
L
L
L
L
LB#/
UB#
X
X
X
X
X
X
X
L
L
L
L
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z Config. reg.
©2007 Micron Technology, Inc. All rights reserved.
2
DQ[15:0]
Data-in or
Bus Operations
Data-out
data-out
Data-in
High-Z
High-Z
High-Z
High-Z
out Z
X
X
X
3
Notes
5, 6
4, 6
4, 8
4, 8
4, 8
4, 8
8, 9
4
4
8
7