NAND64GAH0HZA5E Micron Technology Inc, NAND64GAH0HZA5E Datasheet - Page 13
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NAND64GAH0HZA5E
Manufacturer Part Number
NAND64GAH0HZA5E
Description
Manufacturer
Micron Technology Inc
Datasheet
1.NAND64GAH0HZA5E.pdf
(29 pages)
Specifications of NAND64GAH0HZA5E
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Supplier Unconfirmed
NAND32GAH0H, NAND64GAH0H
5.2
5.3
5.4
Bus topology
The NANDxxxAH0H device supports the MMC protocol. For more details, refer to section
6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC
Standard Specification contains a bus circuitry diagram for reference.
Power-up
The power-up is handled locally in each device and in the bus master.
shows the power-up sequence. Refer to section 12.3 of the JEDEC Standard Specification
No. JESD84-A43 for specific instructions regarding the power-up sequence.
After power-up, the maximum initial load the NANDxxxAH0H can present on the V
C4, in parallel with a minimum of R4. During operation, device capacitance on the V
must not exceed 10 µF
Power cycling
The bus master can execute any sequences of V
However, the master must not issue any commands until V
each operating voltage range. For more information about power cycling see Section 12.3.3
of the JEDEC Standard Specification No. JESD84-A43 and
.
CC
and V
CCQ
CC
Figure 6: Power
and V
power-up/power down.
MultiMediaCard interface
CCQ
Figure 5: Power-up
are stable within
cycling.
CC
CC
line is
13/29
line