M69AW048BL70ZB8T STMicroelectronics, M69AW048BL70ZB8T Datasheet
M69AW048BL70ZB8T
Specifications of M69AW048BL70ZB8T
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M69AW048BL70ZB8T Summary of contents
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FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIMES: 70ns LOW STANDBY CURRENT: 100µA DEEP POWER-DOWN CURRENT: 10µA BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O 8 WORD PAGE ACCESS CAPABILITY: 18ns WIDE OPERATING TEMPERATURE ...
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M69AW048B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 9. Capacitance ...
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... CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW048B is a member of STMicroelectronics PSRAM memory family. These devices are manu- factured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area ...
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Figure 3. TFBGA Connections (Top view through package DQ8 UB A3 DQ9 A5 A6 DQ10 V SS A17 A7 DQ11 V CC DQ12 ...
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M69AW048B SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access dur- ing ...
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Figure 4. Block Diagram INTERNAL CLOCK GENERATOR ADDRESS CONTROL POWER CONTROLLER V SS ARBITRATION LOGIC REFRESH CONTROLLER DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER COLUMN DECODER LOGIC ADDRESS M69AW048B DQ0-DQ7 DQ8-DQ15 AI07221b 7/29 ...
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M69AW048B OPERATION Operational modes are determined by device con- trol inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see 2., Operating Modes). Power-Up Sequence Because the internal control logic of the M69AW048B needs to ...
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Power-Down Configuration data (see 5., Power-Down Configuration cycle is written into a different address, the se- quence is aborted. In the last cycle, a read is made from ...
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M69AW048B Table 4. Power-Down Program Sequence Cycle # Operation 1st 2nd 3rd 4th 5th 6th Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Power-Down Modes DQ15–DQ9 Deep Power-Down (default) 4Mb PAR 8Mb PAR 16Mb PAR Table 6. Power-Down ...
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... Storage Temperature STG V Core Supply Voltage CC V Input or Output Voltage IO these or any other conditions above those indicat the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter M69AW048B Min Max Unit – – ...
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M69AW048B DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under ...
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Table 9. Capacitance Symbol C Input Capacitance on all pins (except DQ Output Capacitance OUT Table 10. DC Characteristics Symbol Parameter I CC1 V Active Current CC I CC2 I V Page Read Current CC3 CC I CCPD ...
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M69AW048B Table 11. Read Mode AC Characteristics Symbol Alt. (1,2) t Address Valid Time t RC AVAX (1,6,7) t Page Read Cycle Time t PRC AVAX2 (1,6,7) t Page Read Cycle Time t PRC AVEH2 t t Address Valid to ...
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Figure 7. Read Mode AC Waveforms A0-A20 tAVEL E1 G LB, UB DQ0-DQ15 Note High High. Figure 8. Output Enable Controlled, Read Mode AC Waveforms tAXAV A0-A20 E1 tAVGL G UB, LB DQ0-DQ15 Note: Write Enable ...
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M69AW048B Figure 9. UB/LB Controlled, Read Mode AC Waveforms tAXAV A0-A20 tAVQV E1 Low tBLQV LB UB tBLQX DQ0-DQ7 DQ8-DQ15 Note Low High Low High. Figure 10. Page Address and Chip Enable ...
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Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms tAXAV A20-A3 tAXAV2 tAVAX ADDRESS A2-A0 VALID tAVQV E Low tGLQV G tBLQV LB, UB tGLQX tBLQX DQ0-DQ15 (Normal Access) Note High. tAVAX ADDRESS VALID tAXAV tAVAX2 ...
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M69AW048B Table 12. Write Mode AC Characteristics Symbol Alt. (1,2) t Write Cycle Time t WC AVAX (2) t Address Valid to LB, UB Low t AS AVBL (2) t Address Valid to Chip Enable Low t AS AVEL (2) ...
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Figure 12. Chip Enable Controlled, Write AC Waveforms A0-A20 tAVEL E1 tAVWL W tAVBL LB, UB tGHEL G DQ0-DQ15 Note High. Figure 13. Write Enable Controlled, Write AC Waveforms tAXAV A0-A20 E1 Low tAVWL W LB, UB tGHAV ...
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M69AW048B Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1 A0-A20 E1 Low tAVWL DQ0-DQ7 DQ8-DQ15 Note High. Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2 tAXAV A0-A20 E1 Low ...
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Figure 16. Write Enable and LB/UB Controlled, Write AC Waveforms 3 tAXAV A0-A20 E1 Low tAVBL DQ0-DQ7 DQ8-DQ15 Note High. Figure 17. Write Enable and LB/UB Controlled, Write AC Waveforms 4 tAXAV A0-A20 E1 Low ...
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M69AW048B Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms A0-A20 tEHAX (read) E1 tEHEL W UB, LB tGHEL G tEHQZ tEHQX READ DATA DQ0-DQ15 OUTPUT Note: Write address is valid from either ...
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Figure 20. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms tAXAV A0-A20 E1 Low W UB tGHQZ tGHQX DATA DQ0-DQ15 OUT Note: E1 can be tied to Low for W and G controlled operation. ...
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M69AW048B Table 13. Standby/Power-Down Mode AC Characteristics Symbol Alt Low Setup Time for Power Down Entry CLEX CSP Low Hold Time after Power Down Entry EXCH C2LP E1 High Hold Time following E2 High ...
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Figure 23. Power-Down Mode AC Waveforms E1 E2 DQ0-D15 Figure 24. Power-Up Mode AC Waveforms E1 E2 VDD Figure 25. Standby Mode Entry AC Waveforms, After Read Note High. tCLEX tEXCH Power-Down Power-Down Mode Entry ...
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M69AW048B PACKAGE MECHANICAL Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View FD FE BALL "A1" Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm ...
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PART NUMBERING Table 15. Ordering Information Scheme Example: Device Type M69 = PSRAM Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 048 = 32 Mbit (2M x16) Option Chip Enable Option ...
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M69AW048B REVISION HISTORY Table 16. Document Revision History Date Version 07-Oct-2002 -01 First Issue 10-Mar-2003 2.0 Document completely revised Data Key and Address Key renamed Power-Down Configuration data and Power-Down Configuration Address respectively. Sleep mode renamed Deep Power-Down mode. I ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...