M69AW048BL70ZB8T STMicroelectronics, M69AW048BL70ZB8T Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
M69AW048BL70ZB8T
Manufacturer Part Number
M69AW048BL70ZB8T
Description
Manufacturer
STMicroelectronics
Datasheet
1.M69AW048BL70ZB8T.pdf
(29 pages)
Specifications of M69AW048BL70ZB8T
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
M69AW048B
SUMMARY DESCRIPTION
The M69AW048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 2.7V to 3.3V
supply voltage range.
M69AW048B is a member of STMicroelectronics
PSRAM memory family. These devices are manu-
factured using dynamic random access memory
cells, to minimize the cell size, and maximize the
amount of memory that can be implemented in a
given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AW048B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Figure 2. Logic Diagram
4/29
A0-A20
UB
E1
E2
LB
W
G
21
M69AW048B
V CC
V SS
16
DQ0-DQ15
AI05844c
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features various kinds of Power-Down
modes for power saving as a user configurable op-
tion:
Table 1. Signal Names
A0-A20
DQ0-DQ15
E1, E2
G
W
UB
LB
V
V
NC
CC
SS
The Partial Array Refresh (PAR) performs a
limited refresh of the part of the PSRAM array
(4 Mbits, 8 Mbits, 16Mbits) that contains
essential data.
Deep Power-Down mode: this mode achieves
a very low current consumption by halting all
the internal activities. Since the refresh
circuitry is halted, the duration of the power-
down should be less than the maximum period
for refresh.
Address Input
Data Input/Output
Chip Enable, Power Down
Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable
Supply Voltage
Ground
Not Connected
(no internal connection)