MPC2605ZP66 Freescale, MPC2605ZP66 Datasheet - Page 12

• Manufacturer Part Number: MPC2605ZP66
• Manufacturer: Freescale

Specifications of MPC2605ZP66

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
systems such as these, transactions generated by the
DMA bridge are true memory requests that have data
tenures associated with them. These are called snoop
data tenures. Because these two types of systems are
fundamentally different, the MPC2605 must know in
which type of system it is resident in order to respond
properly to the different types of transactions. For
systems that do not have snoop data tenures, CFG3
must be tied high. For systems that do use snoop data
tenures, CFG3 must be tied low.
CFG4
the memory controller that a cache hit has been
detected, it is taking control of the address and data
tenures of the transaction (see 60x BUS
OPERATION and MEMORY COHERENCE).
This means that the MPC2605 will assert AACK to
end the address tenure, and it will assert TA as needed
for the data tenure. If the data bus is idle when a
processor request is initiated, the MPC2605 will assert
AACK the cycle after TS was asserted. If the data bus
is busy when the request is made, the MPC2605 will
wait until the outstanding data tenure has completed
before asserting AACK. By holding off on the
assertion of AACK, the MPC2605 enforces the policy
of, at most, two outstanding data transactions at any
one time. Tying CFG4 low prevents the MPC2605
from asserting AACK to end transactions, for which it
has asserted L2 CLAIM. In systems that tie CFG4 low,
it is necessary for the memory controller to assert
AACK for all transactions. This allows the DMA
bridge to initiate snoop transactions (as defined later)
even when there are two outstanding data transactions.
If this type of system is implemented, the arbiter must
ensure that the processor's bus grant is negated once
there are two outstanding data transactions. It is
expected that most systems will tie CFG4 high.
RESET/INITIALIZATION
functionality, the HRESET pin of the MPC2605
should be connected to the same signal that is used to
reset the processor. When HRESET is negated, the
MPC2605 commences an internal initialization
sequence to clear all of the valid bits in the cache. The
sequence takes approximately 4000 clock cycles.
During this time the MPC2605 will not participate in
any bus transaction that occurs. All transactions are,
12
When the MPC2605 asserts L2 CLAIM to signal to
To ensure proper initialization and system
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
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however, monitored so that, regardless of when the
initialization sequence completes, the MPC2605 is
prepared to take action on the next transaction initiated
by the processor.
MPC2605 will detect its first cache hit. At this time
the system will experience its first assertion of
L2 CLAIM. If the memory controller must be
configured via software to comprehend assertions of
L2 CLAIM, this configuration operation must be
completed by this time. For systems that cannot
guarantee that this requirement is met, it is necessary
to disable the MPC2605 until such time as this
configuration can be guaranteed. Disabling the
MPC2605 can be accomplished by asserting
L2 UPDATE INH sometime during reset and negating
it when it is deemed safe for caching to commence.
60x BUS OPERATION
tenure. An address tenure is a set number of bus cycles
during which the address bus and its associated control
signals are being used for the transaction at hand. In
general, there are two types of transactions: those that
only have address tenures, called address-only
transactions; and those that require the use of the data
bus; and therefore, will have a data tenure. These
transactions are called data transactions. This section
describes how address and data tenures are defined as
viewed by the MPC2605.
Address Tenures
defined. They start with an assertion of TS by a device
that has been granted the bus by the system arbiter.
This device is called the bus master for this
transaction. At the same time that TS is asserted, the
bus master also drives the address and all other
relevant control signals that define the transaction.
is only asserted for one cycle, but all other signals are
held valid by the bus master until some other device
asserts AACK. The device that asserts AACK
becomes the slave for this transaction. Typically, the
slave is the memory controller, although for
transactions that are cache hits, the MPC2605
becomes the slave by driving L2 CLAIM.
bus by asserting ARTRY. ARTRY may be asserted at
any time after TS is asserted, but must be held through
At some point after this 4000-cycle sequence, the
All transactions have what is called an address
Address tenures on the 60x bus are fairly well
Transactions can be aborted by any device on the
MOTOROLA
TS