MPC2605ZP66 Freescale, MPC2605ZP66 Datasheet - Page 16

• Manufacturer Part Number: MPC2605ZP66
• Manufacturer: Freescale

Specifications of MPC2605ZP66

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
the L2 BR signal is sampled first. If L2 BR is already
asserted, then it is clear that another device is also in a
castout situation. The late device will wait until L2 BR
is negated before continuing in its attempt to perform a
castout.
assertions of ARTRY, it is possible for a situation to
arise where device two is waiting for device one to do
its castout before asserting L2 BR. If there is an
assertion of ARTRY by a device other than device one,
device one is required to negate L2 BR in the BR
window. In order to prevent device two from
interpreting device one's negation of L2 BR as an
indication that device one has completed its castout, a
simple arbitration mechanism is used. All devices
have a simple two-bit counter that is synchronized
such that all counters always have the same value. For
the purposes of performing a castout operation, a
given pair can only assert L2 BR if the counter is equal
to its value of CFG[1:2]. This simple mechanism
prevents more than one device from asserting L2 BR
in the same cycle and therefore, not being cognizant of
the another device's need to perform a castout.
Snoop Hit Before Castout
shared bus request occurs when a snoop hits a dirty
line in one of the MPC2605 devices. If device one has
a cache line in its COB, it will assert L2 BR so that it
may perform a castout operation. If a snoop hits a dirty
line in device two, it will assert both ARTRY and
L2 BR so that it can write the snoop data back to main
memory. When device one detects that ARTRY has
been asserted, it needs to be made aware that device
two needs to request the bus. Otherwise, at the same
time that device two is asserting L2 BR, device one
will attempt to conform to the BR window protocol
and negate L2 BR. This situation is avoided by device
one sampling FDN when it detects that ARTRY has
been asserted. If FDN is asserted at the same time as
ARTRY is asserted, device one will recognize that
device two is asserting ARTRY. Device one will then
High-Z L2 BR, so that there will not be contention
when device two is asserting L2 BR.
MULTIPROCESSING
up to four processors. For each processor, there is a
bus request, bus grant, and data bus grant signal pin on
16
Because of the BR window protocol associated with
The other situation that can cause problems with a
The MPC2605 can be used as a common cache for
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
Go to: www.freescale.com
the MPC2605. Each of these pins need to be connected
to the respective processor's arbitration signals in the
system.
processor. Thus, the same restrictions on pipelining
depth are true with regard to how many processor
transactions can be outstanding at any one time. There
can only be one data transaction from any processor
pipelined on top of a current data transaction that was
issued by any processor.
performed in the same order as the address tenures on
a system-wide basis. If processor one makes a request
and then processor two makes a request, processor
one's data tenure must precede processor two's data
tenure. Note that this is not a 60x bus restriction, but
rather a restriction necessary for proper operation of
the MPC2605.
of multiple processors as defined by the MESI
(modified-exclusive-shared-invalid) protocol without
actually implementing the protocol. This is possible
for two reasons. Since the MPC2605 is a look-aside
cache, all transactions are monitored by all devices on
the bus. Also, the MPC2605 cannot, on its own,
modify data. Thus, if one processor requests exclusive
access to a cache line, it is not necessary for the
MPC2605 to invalidate its copy of the data, as would
be required under the MESI protocol. If a second
processor requests the same data, the transaction will
cause the first processor to assert ARTRY. This will
prevent the MPC2605 from supplying stale data to the
second processor.
taken when parking the data bus in Fast L2 mode. By
the nature of MP systems running under the MESI
protocol, there will be assertions of ARTRY to abort
cache read hits. Thus, in an MP system, the data bus
cannot be parked to any processor if the system is to
be run in Fast L2 mode.
PWRDN
to go into a low-power sleep state. This state is entered
after PWRDN is synchronized and both the address
and data buses are idle. All data is retained while in the
sleep state.
PWRDN is dependent on the state of WT at the rising
The MPC2605 treats multiple processors as one
The data tenures for all processors must be
The MPC2605 keeps coherent with the L1 caches
As discussed in Data Bus Parking, care must be
An assertion of PWRDN will cause the MPC2605
The behavior of the MPC2605 on negation of
MOTOROLA