5962-8680502QA QP SEMICONDUCTOR, 5962-8680502QA Datasheet - Page 8

• Manufacturer Part Number: 5962-8680502QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8680502QA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
4.3.1 Group A inspection.
c.
a.
b.
c.
DEFENSE SUPPLY CENTER COLUMBUS
Tests shall be as specified in table II herein.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
Subgroup 4 (C
changes which may affect input or output capacitance. Sample size is 15 devices, all input and output terminals tested
and no failures.
A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps
performed in the listed sequence.
MICROCIRCUIT DRAWING
Margin test method A. (Steps 1 through 4 may be performed at the wafer level.)
(1) Program at +25°C with a greater than 95 percent pattern (example, diagonal "1's")(see 3.10.2 and 3.10.3).
(2) Unbiased bake for 24 hours at +175°C.
(3) Test at T
(4) Erase.
(5) Program at +25°C with a checkerboard pattern (see 3.10.2 and 3.10.3)
(6) Test at T
(7) Burn-in (see 4.2A).
(8) Test at T
(9) Test at T
(10) Test at T
(11) Erase (see 3.10.1). Devices may be submitted for groups A, B, C, and D testing prior to erasure provided
(12) Verify erasure at +25°C (see 3.10.3).
Margin test method B. (Steps 1 through 3 may be performed at the wafer level.)
(1) At +25°C program greater than 95 percent of the bit locations, including the slowest programming cell.
(2) Bake unbiased for 72 hours at +140°C or for 48 hours at 150°C or for 8 hours at 200°C or, for
(3) At +25°C perform a margin test using V
(4) Perform dynamic burn-in in accordance with 4.2a.
(5) At +25°C perform a margin test using V
(6) Perform electrical test in accordance with 4.2b.
(7) Repeat steps 5 and 6 at T
(8) Erase per 3.10.1. Devices may be submitted to quality conformance inspection.
(9) Verify erasure in accordance with 3.10.3.
COLUMBUS, OHIO 43218-3990
(i.e., t
the devices have been 100 percent seal tested in accordance with method 5004 of MIL-STD-883.
unassembled devices only, 72 hours at 225°C. The maximum unbiased bake temperature shall not exceed
+200°C for packaged devices or +300°C for unassembled devices.
STANDARD
AVQV
IN
and C
C
C
C
C
C
= 1 µs).
= +25°C minimum (see 3.10.3), including a margin test at Vm = +6 V and loose timing
= +25°C (minimum), including a margin test at Vm = +6 V and loose timing (i.e., t
= +25°C (see 3.10.3), including a margin test at Vm = +6 V and loose timing (i.e., t
= +125°C (minimum), including a margin test at Vm = +6 V and loose timing (i.e., t
= -55°C, including a margin test at Vm = +6 V and loose timing (i.e., t
OUT
measurements) shall be measured only for the initial test and after process or design
C
= 125°C and -55°C.
M
M
= +5.8 V to loose timing (i.e., t
= +5.8 V to loose timing (i.e., t
SIZE
A
REVISION LEVEL
AA
AA
= 1µs).
= 1µs).
F
AVQV
= 1 µs).
AVQV
SHEET
AVQV
AVQV
5962-86805
= 1 µs).
= 1 µs).
= 1 µs).
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