CY7C0853V-100BBI Cypress Semiconductor Corp, CY7C0853V-100BBI Datasheet - Page 17

• Manufacturer Part Number: CY7C0853V-100BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBI

• Density: 9Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 310mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06070 Rev. *H
22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
24. The output is disabled (high-impedance state) by CE = V
25. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
Numbers are for reference only.
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
ADDRESS
DATA
B0–B3
R/W
CLK
OUT
OE
CE
t
RSF
t
t
t
t
SW
SA
SB
SC
A
n
t
RS
t
t
t
t
HB
HW
HA
t
HC
CH2
1 Latency
t
INACTIVE
RSS
t
CYC2
t
RSR
t
CKLZ
t
CL2
Figure 9. Read Cycle
IH
A
following the next rising edge of the clock.
n+1
Figure 8. Master Reset
ACTIVE
t
CD2
IL
with CNT/MSK = V
[4, 22, 23, 24, 25]
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
DC
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
t
OE
Page 17 of 32
Q
n+2
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