CY7C0853V-100BBI Cypress Semiconductor Corp, CY7C0853V-100BBI Datasheet - Page 25

• Manufacturer Part Number: CY7C0853V-100BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBI

• Density: 9Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 310mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06070 Rev. *H
39. CE
40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
41. If t
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t
CLK
L_PORT
ADDRESS
R/W
L_PORT
DATA
CLK
R_PORT
ADDRESS
R/W
R_PORT
DATA
CCS
0
= OE = ADS = CNTEN = B0 – B3 = LOW; CE
L
L
R
R
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t
IN
OUT
t
CKHZ
t
CH2
t
t
CH2
CYC2
Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read
t
t
CYC2
CL2
t
SW
(continued)
t
t
SD
SA
t
CL2
D
A
n
n
1
t
HA
= CNTRST = MRST = CNT/MSK = HIGH.
t
CCS
t
SA
t
HW
t
HD
A
n
t
HA
t
CKLZ
t
CYC2
DC
t
CD2
+ t
CD2
) after the rising edge of R_Port's clock.
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
CYC2
CCS
Q
+ t
n
is violated, indeterminate data is Read out.
CD2
) after the rising edge of R_Port's clock. If t
[39, 40, 41]
Page 25 of 32
CCS
[+] Feedback