AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 21

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

RCF Decimation Register
Each RCF channel can be used to decimate the data rate. The
decimation register is an 8-bit register and can decimate from 1
to 256. The RCF decimation is stored in 0xA0 in the form of
M
RCF Decimation Phase
The RCF decimation phase can be used to synchronize multiple
filters within a chip. This is useful when using multiple channels
within the AD6624 to implement polyphase filter allowing the
resources of several filters to be operated in parallel and shared.
In such an application, two RCF filters would be processing the
same data from the CIC5. However, each filter will be delayed
by one-half the decimation rate, thus creating a 180° phase
difference between the two halves. The AD6624 filter channel
uses the value stored in this register to preload the RCF counter.
Therefore, instead of starting from 0, the counter is loaded with
this value, thus creating an offset in the processing that should
be equivalent to the required processing delay. This data is
stored in 0xA1 as an 8-bit number.
RCF Filter Length
The maximum number of taps this filter can calculate, N
given by the equation below. The value N
the channel register within the AD6624 at address 0xA2.
The RCF coefficients are located in addresses 0x00 to 0x7F and
are interpreted as 20-bit two’s-complement numbers. When
writing the coefficient RAM, the lower addresses will be mul-
tiplied by relatively older data from the CIC5, and the higher
coefficient addresses will be multiplied by relatively newer data
from the CIC5. The coefficients need not be symmetric and the
coefficient length, N
are symmetric, both sides of the impulse response must be writ-
ten into the coefficient RAM.
Although the base memory for coefficients is only 128 words
long, the actual length is 256 words. There are two pages, each
of 128 words. The page is selected by Bit 8 of 0xA4. Although
this data must be written in pages, the internal core handles
filters that exceed the length of 128 taps. Therefore, the full
length of the data RAM may be used as the filter length (160 taps).
The RCF stores the data from the CIC5 into a 160 × 40 RAM.
160 × 20 is assigned to I data and 160 × 20 is assigned to Q
data. The RCF uses the RAM as a circular buffer, so that it is
difficult to know in which address a particular data element is
stored. To avoid start-up transients due to undefined data RAM
values, the data RAM should be cleared upon initialization.
REV. B
RCF
N
TAPS
-1. The input rate to the RCF is f
Figure 27. RAM Coefficient Filter Block Diagram
≤
min
I IN
Q IN



f
CLK
TAPS
f
SAMP
160 20b
256 20b
160 20b
×
C-RAM
Q-RAM
I-RAM
, may be even or odd. If the coefficients
M
5
RCF
,
160



SAMP5
TAPS
Q OUT
I OUT
.
–1 is written to
TAPS
(13)
, is
–21–
When the RCF is triggered to calculate a filter output, it starts
by multiplying the oldest value in the data RAM by the first
coefficient, which is pointed to by the RCF Coefficient Offset
Register (0xA3). This value is accumulated with the products
of newer data words multiplied by the subsequent locations
in the coefficient RAM until the coefficient address
RCF
Coefficient Address
0
1
2 (N
The RCF Coefficient Offset register can be used for two pur-
poses. The main purpose of this register is to allow multiple
filters to be loaded into memory and selected simply by chang-
ing the offset as a pointer for rapid filter changes. The other use
of this register is to form part of symbol timing adjustment. If
the desired filter length is padded with zeros on the ends, the
starting point can be adjusted to form slight delays when the
filter is computed with reference to the high-speed clock. This
allows for vernier adjustment of the symbol timing. Course
adjustments can be made with the RCF Decimation Phase.
The output rate of this filter is determined by the output rate of
the CIC5 stage and M
RCF Output Scale Factor and Control Register
Register 0xA4 is a compound register used to configure several
aspects of the RCF register. Bits 3–0 are used to set the scale of
the fixed-point output mode. This scale value may also be used
to set the floating-point outputs in conjunction with Bit 6 of
this register.
Bits 4 and 5 determine the output mode. Mode 00 sets up the
chip in fixed-point mode. The number of bits is determined by
the serial port configuration. See Serial Output Data Port section.
Mode 01 selects floating-point mode 8 + 4. In this mode, an 8-bit
mantissa is followed by a 4-bit exponent. In mode 1x (x is don’t
care), the mode is 12 + 4, or 12-bit mantissa and 4-bit exponent.
Normally, the AD6624 will determine the exponent value that
optimizes numerical accuracy. However, if Bit 6 is set, the value
stored in Bits 3–0 is used to scale the output. This ensures con-
sistent scaling and accuracy during conditions that may warrant
predictable output ranges.
If Bit 7 is set, the same exponent will be used for both the real
and imaginary (I and Q) outputs. The exponent used will be the
one that prevents numeric overflow at the expense of small
signal accuracy. However, this is seldom a problem as small
numbers would represent 0 regardless of the exponent used.
f
SAMPR
TAPS
OFF
+ N
– 1)
=
f
M
SAMP
TAPS
RCF
Table VI. Output Mode Formats
Floating Point 12 + 4
Floating Point 8 + 4
Fixed Point
–1 is reached.
5
Table V. Three-Tap Filter
RCF
Impulse Response
h(0)
h(1)
h(2)
.
1x
01
00
AD6624
Data
N(0) Oldest
N(1)
N(2) Newest
(14)