AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 30

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

AD6624
0x80: Channel Sleep Register
This register contains the SLEEP bit for the channel. When this
bit is high, the channel is placed in a low power state. When this bit
is low, the channel processes data. Note that in serial slave mode,
the RESET pin needs to be held low for several SCLK cycles to
ensure that it will program this bit high. This bit can also be set
by accessing the SLEEP register at external address 3. When
the external SLEEP register is accessed, all four channels are
accessed simultaneously and the SLEEP bits of the channels are
set appropriately.
0x81: Soft_SYNC Register
This register is used to initiate SYNC events through the micro-
port. If the Hop bit is written high, the Hop Hold-Off Counter
at address 0x84 is loaded and begins to count down. When this
value reaches one, the NCO Frequency register used by the NCO
accumulator is loaded with the data from channel addresses 0x85
and 0x86. When the Start bit is set high, the Start Hold-Off
Counter is loaded with the value at address 0x83 and begins to
count down. When this value hits one, the Sleep bit in address
0x80 is dropped low and the channel is started.
0x82: Pin_SYNC Register
This register is used to control the functionality of the SYNC
pins. Any of the four SYNC pins can be chosen and monitored
by the channel. The channel can be configured to initiate either
a Start or Hop SYNC event by setting the Hop or Start bit high.
These bits function as enables so that when a SYNC pulse occurs
either the Start or Hop Hold-Off Counters are activated in the
same manner as with a Soft_SYNC.
0x83: Start Hold-Off Counter
The Start Hold-Off Counter is loaded with the value written to
this address when a Start_Sync is initiated. It can be initiated by
either a Soft_SYNC or Pin_SYNC. The counter begins dec-
rementing and when it reaches a value of one, the channel is
brought out of SLEEP and begins processing data. If the chan-
nel is already running, the phase of the filters is adjusted such
that multiple AD6624s can be synchronized. A periodic pulse
on the SYNC pin can be used in this way to adjust the timing of
the filters with the resolution of the ADC sample clock. If this
register is written to a one, the Start will occur immediately
when the SYNC comes into the channel. If it is written to a
zero, no SYNC will occur.
0x84: NCO Frequency Hold-Off Counter
The NCO Frequency Hold-Off Counter is loaded with the value
written to this address when either a Soft_SYNC or Pin_SYNC
comes into the channel. The counter begins counting down so
that when it reaches one, the NCO Frequency word is updated
with the values of addresses 0x85 and 0x86. This is known as a
Hop or Hop_SYNC. If this register is written to a one, the NCO
Frequency will be updated immediately when the SYNC comes
into the channel. If it is written to a zero, no HOP will occur.
NCO HOPs can be either phase continuous or nonphase con-
tinuous, depending upon the state of Bit 3 of the NCO control
register at channel address 0x88. When this bit is low, the Phase
Accumulator of the NCO is not cleared, but starts to add the
new NCO Frequency word to the accumulator as soon as the
SYNC occurs. If this bit is high, the Phase Accumulator of the
NCO is cleared to zero and the new word is then accumulated.
–30–
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO Frequency
word. These bits are shadowed and are not updated to the regis-
ter used for the processing until the channel is either brought
out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued.
In the latter two cases, the register is updated when the Fre-
quency Hold-Off Counter hits a value of one. If the Frequency
Hold-Off Counter is set to one, the register will be updated as
soon as the shadow is written.
0x86: NCO Frequency Register 1
This register represents the 16 MSBs of the NCO Frequency word.
These bits are shadowed and are not updated to the register used
for the processing until the channel is either brought out of SLEEP
or a Soft_SYNC or Pin_SYNC has been issued. In the latter
two cases, the register is updated only when the Frequency
Hold-Off Counter hits a value of one. If the Frequency Hold-
Off Counter is set to one, the register will be updated as soon as
the shadow is written.
0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It can
be interpreted as values ranging from 0 to just under 2 π.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the channel.
The bits are defined below. For more detail, the NCO section
should be consulted.
Bits 8–7 of this register choose which of the four SYNC pins are
used by the channel. The SYNC pin selected can be used to
initiate a START, HOP, or timing adjustment to the channel.
The Synchronization section of this data sheet provides more
details on this.
Bit 6 of this register defines whether the A or B Input Port is used
by the channel. If this bit is low, the A Input Port is selected; if
this bit is high, the B Input Port is selected. Each input port
consists of a 14-bit input mantissa (INx[13:0]), a 3-bit exponent
(EXPx[2:0]), and an input enable pin, IENx. The x represents
either A or B.
Bits 5–4 determine how the sample clock for the channel is
derived from the high-speed CLK signal. There are four pos-
sible choices. Each is defined below but for further detail, the
NCO section of the data sheet should be consulted.
When these bits are 00, the input sample rate (f
channel is equal to the rate of the high-speed CLK signal. When
IEN is low, the data going into the channel is masked to 0. This
is an appropriate mode for TDD systems where the receiver
may wish to mask off the transmitted data yet still remain in the
proper phase for the next receive burst.
When these bits are 01, the input sample rate is determined by
the fraction of the rising edges of CLK on which the IEN input
is high. For example, if IEN toggles on every rising edge of
CLK, then the IEN signal will only be sampled high on one out
of every two rising edges of CLK. This means that the input
sample rate f
When these bits are 10, the input sample rate is determined by
the rate at which the IEN pin toggles. The data that is captured
on the rising edge of CLK after IEN transitions from low to
SAMP
will be 1/2 the CLK rate.
SAMP
) of the
REV. B