ISP1760ET STEricsson, ISP1760ET Datasheet - Page 34

• Manufacturer Part Number: ISP1760ET
• Manufacturer: STEricsson

Specifications of ISP1760ET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 15.
[1]
Table 17.
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
USBCMD - USB Command register (address 0020h) bit allocation
USBSTS - USB Status register (address 0024h) bit allocation
8.2.2 USBSTS register
LHCR
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
Table 16.
[1]
The USB Status (USBSTS) register indicates pending interrupts and various states of the
host controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears register bits by writing ones to them. The bit allocation is
given in
Bit
31 to 8
7
6 to 2
1
0
For details on register bit description, refer to
Universal Serial Bus Rev.
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
Table
Symbol
-
LHCR
-
HCRESET Host Controller Reset: This control bit is used by the software to reset
RS
USBCMD - USB Command register (address 0020h) bit description
17.
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Description
reserved
Light Host Controller Reset (optional): If implemented, it allows the
driver software to reset the EHCI controller without affecting the state of
the ports or the relationship to the companion host controllers. If not
implemented, a read of this field will always return logic 0.
reserved
the host controller.
Run/Stop: 1 = Run, 0 = Stop. When set, the host controller executes the
schedule.
Rev. 04 — 4 February 2008
1.0”.
reserved
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
[1]
reserved
reserved
reserved
reserved
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
R/W
27
19
11
27
0
1
1
3
0
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
HCRESET
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
1
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1760
R/W
R/W
R/W
R/W
R/W
RS
33 of 110
24
16
24
0
0
8
1
0
0
0