ISP1760ET STEricsson, ISP1760ET Datasheet - Page 96

• Manufacturer Part Number: ISP1760ET
• Manufacturer: STEricsson

Specifications of ISP1760ET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1760_4
Product data sheet
14.2.3 Multi-cycle: DMA read
Table 99.
T
Symbol Parameter
V
t
t
t
t
T
t
t
t
V
t
t
t
t
T
t
t
t
a16
a26
d16
w16
a36
a46
h16
a16
a26
d16
w16
a36
a46
h16
amb
Fig 21. DMA read (multi-cycle burst)
cy16
cy16
CC(I/O)
CC(I/O)
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
DREQ and DACK are active HIGH.
DACK assertion after DREQ assertion time
RD_N assertion after DACK assertion time
data valid time after RD_N assertion
RD_N pulse width
read-to-read cycle time
DREQ de-assertion time after last burst RD_N
de-assertion
DACK de-assertion to next DREQ assertion
time
data hold time after RD_N de-asserts
DACK assertion after DREQ assertion time
RD_N assertion after DACK assertion time
data valid time after RD_N assertion
RD_N pulse width
read-to-read cycle time
DREQ de-assertion time after last burst RD_N
de-assertion
DACK de-assertion to next DREQ assertion
time
data hold time after RD_N de-asserts
DMA read (multi-cycle burst)
DREQ
DACK
RD_N
DATA
Rev. 04 — 4 February 2008
t
a16
t
a26
t
d16
t
w16
data 0
T
t
h16
cy16
Embedded Hi-Speed USB host controller
data 1
Min
0
0
-
38
46
-
-
-
0
0
-
17
38
-
-
-
data n-1
t
a36
data n
Max
-
-
31
-
-
30
82
5
-
-
16
-
-
20
82
5
t
a46
004aaa531
© NXP B.V. 2008. All rights reserved.
ISP1760
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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