W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 38

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

6.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
BIT
0
0
0
1
0
0
3
out interrupt is pending.
this bit will be set to a logical 0.
BIT
2
0
1
1
1
0
0
ISR
BIT
1
0
1
0
0
1
0
BIT
1
0
0
0
0
0
0
7
INTERRUPT
PRIORITY
TABLE 6-4 INTERRUPT CONTROL FUNCTION
Second
Second
Fourth
6
Third
First
-
0
5
4
0
TBR Empty
INTERRUPT
UART
Receive
Status
RBR Data
Ready
FIFO Data
Timeout
Handshake
status
-
3
TYPE
INTERRUPT SET AND FUNCTION
2
-38-
1
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for
4 characters period of time
since last access of RX
FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
reached
0
INTERRUPT SOURCE
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
2. PBER =1
4. TDCD = 1
2. TDSR = 1
W83627SF
-
Read USR
1. Read RBR
2. Read RBR
until FIFO
data under
active level
Read RBR
1. Write data
into TBR
2. Read ISR
if priority is
third)
Read HSR
INTERRUPT
CLEAR