W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 42

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

7.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)
Power on default <7:0> = 00000000 binary
7.1.5 Bank0.Reg4 - CIR Control Register (CTR)
Power on default <7:0> = 0010,1001 binary
BIT
BIT
7-6
5-4
7-5
4-0
3
2
1
0
BNK_SEL<1:0>
RX_FSL<4:0>
RX_FR<2:0>
TMR_CLK
RXFTL1/0
TMR_TST
RXF_RST
EN_TMR
NAME
NAME
READ/WRITE
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bank Select Register. These two bits are shared same
address so that Bank Select Register (BSR) can be
programmed to desired Bank in any Bank.
BNK_SEL<1:0> = 00 Select Bank 0.
BNK_SEL<1:0> = 01 Select Bank 1.
BNK_SEL<1:0> = Reserved.
BNK_SEL<1:0> = Reserved.
Receiver FIFO Threshold Level. It is to determine the
RXTH_I to become 1 when the Receiver FIFO
Threshold Level is equal or larger than the defined value
shown as follow.
RXFTL<1:0> = 00 -- 1 byte
RXFTL<1:0> = 01 -- 4 bytes
RXFTL<1:0> = 10 -- 8 bytes
RXFTL<1:0> = 11 -- 14 bytes
Timer Test. Write to 1, then reading the TMRL/TMRH
will return the programmed values of TMRL/TMRH, that
is, does not return down count counter value. This bit is
for test timer register.
Enable timer. Write to 1, enable the timer
Setting this bit to a logical 1 resets the RX FIFO counter
logic to initial state. This bit will clear to a logical 0 by
itself after being set to a logical 1.
Timer input clock.
Winbond test register
Receiver Frequency Range 2~0. These bits select the
input frequency of the receiver ranges. For the input
signal, that is through a band pass filter, i.e., the
frequency of the input signal is located at this defined
range then the signal will be received.
Receiver Frequency Select 4~0. Select the receiver
operation frequency.
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DESCRIPTION
DESCRIPTION
W83627SF