NH82801DBSL8DE 869490 Intel, NH82801DBSL8DE 869490 Datasheet - Page 359
NH82801DBSL8DE 869490
Manufacturer Part Number
NH82801DBSL8DE 869490
Description
Manufacturer
Intel
Datasheet
1.NH82801DBSL8DE_869490.pdf
(587 pages)
Specifications of NH82801DBSL8DE 869490
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9.8.3.6
Intel
®
82801DB ICH4 Datasheet
LV2 — Level 2 Register
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
7:5
3:1
Bit
7:0
4
0
THRM_DTY — R/W . This write-once 3-bit field determines the duty cycle of the throttling when the
thermal override condition occurs. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024
PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the C2 state, no
throttling occurs.
There is no enable bit for thermal throttling, because it should not be disabled. Once the
THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active.
THRM_DTY
000
001
010
011
100
101
110
111
THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-controlled
STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
THTL_DTY — R/W. This 3-bit field determines the duty cycle of the throttling when the THTL_EN bit
is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted
(low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.
THTL_DTY
000
001
010
011
100
101
110
111
Reserved
Reads to this register return all zeros, writes to this register have no effect. Reads to this register
generate a “enter a level 2 power state” (C2) to the clock control logic. This will cause the STPCLK#
signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or
THRM# override) will be ignored.
PMBASE + 14h
(
00h
No
Core
ACPI P_BLK+4)
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
Description
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
PCI Clocks
512
896
768
640
512
384
256
128
PCI Clocks
512
896
768
640
512
384
256
128
RO
8 bit
ACPI or Legacy
359
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