NH82801DBSL8DE 869490 Intel, NH82801DBSL8DE 869490 Datasheet - Page 476

• Manufacturer Part Number: NH82801DBSL8DE 869490
• Manufacturer: Intel

Specifications of NH82801DBSL8DE 869490

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D31:F5)
14.1.18
14.1.19
476
Note: The value in this register must only be modified prior to any AC ’97 codec accesses.
INTR_PN—Interrupt Pin Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt pin is used for the AC '97 module interrupt. The AC '97
interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
PCID—Programmable Codec ID Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3
Bit
7:3
2:0
7:4
3:2
1:0
Bit
Reserved.
Interrupt Pin (INT_PN) — RO. Hardwired to 010b to select PIRQB#.
Reserved.
Tertiary Codec ID (TID) — R/W. These bits define the encoded ID that is used to address the
tertiary codec I/O space. Bit 1 is the first bit sent and Bit 0 is the second bit sent on
AC_SDATA_OUT during slot 0.
Secondary Codec ID (SCID) — R/W. These two bits define the encoded ID that is used to address
the secondary codec I/O space. The two bits are the ID that will be placed on slot-0, bits 0 and 1,
upon an I/O access to the secondary codec. Bit 1 is the first bit sent and bit 0 is the second bit sent
on AC_SDATA_OUT during slot 0.
3Dh
02h
No
40h
09h
No
HOT
to D0 transition.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
RO
8 bits
Core
R/W
8 bits
Core
®
82801DB ICH4 Datasheet