NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 19

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

Documentation Changes
Documentation Changes
1.
2.
Note:
3.
4.
5.
Specification Update
SATA Interlock Switch State (ISS) Bit Clarification
The following change applies to Section 14.4.3.7 of the Datasheet.
GPIO34 Power Well Correction
GPIO34 is in the VccHDA power rail. Table 2-22 of the Datasheet is updated as follows:
13. The tolerance of this pin is determined by the voltage of VccHDA either 3.3 V or 1.5 V.
LAN Device Initialization Register
LAN Device Initialization Register 1 is abbreviated as LDR1 (not LDR2). This change
applies to Section 12.2.6 of the Datasheet.
HPET Timer
The following change applies to Section 5.17.1 of the Datasheet
The main counter is clocked by the 14.31818 MHz clock, synchronized into the
domain.
Add GPIO Signal Reset Notes
Add the following notes to Section 2.22 of the Datasheet above Table 2-22.
GPIO Reset Notes:
1. GPIO Configurations registers within the Core Well are reset whenever PWROK is de-
asserted.
2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is
asserted, CF9 reset (06h or 0Eh) event occurs, or SYS_RST# is asserted.
GPIO34
13
Name
Interlock Switch State (ISS)— RO. For systems that support interlock switches
(via CAP.SIS [ABAR+00h:bit28]), if an interlock switch exists on this port (via ISP in
this register), this bit indicates the current state of the interlock switch. A 0 indicates
the switch is closed, and a 1 indicates the switch is opened.
For systems that do not support interlock switches (CAP.SIS=0), this bit reports 0.
Type
I/O
1.5 V
Tolerance
/ 3.3 V
VccHDA
Power
Well
Default
GPO
Mobile: Multiplexed with
HDA_DOCK_RST#.
Desktop: UnMultiplexed
See Note 13.
Description
125 MHz
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