NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 4

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

Revision History
4
Revision
-001
-002
-003
-004
-005
-006
-007
-008
-009
-010
-011
• Initial Release
• Added 82801IO ICH9DO specifications
• Added following Errata
• Added:
• - Errata: 6-
• - Specification Clarifications: 1-
• Added:
• - Errata: 8-PET Alerts on SMBus
• - Specification Changes: 1-t212 Change, 2-LANRST# Timing, 3-Removing
• - Specification Clarifications: 2-DC Characteristics Clarifications, 3-USB
• - Document Changes: 1-PWROK Description Correction, 2-SMBus/SMLink
• Added:
• - Specification Changes: 4-
• - Specification Clarifications: 4-
• - Document Changes:7-
• Added:
• - Errata: 9-SMBus Host Controller May Hang
• - Specification Clarifications: 5-Causes of SMI# /SCI Clarifications, 6-SATA
• - Document Changes: 8-HPET Address Range Correction
• Not released, to synchronize with the specification update posting schedule
• Added:
• - Errata: 10-SATA Gen1 Initialization / LPM Erratum
• - Specification Changes:5-SATA Port Multipliers Removal, 6-CF9 Lock Bit
• - Document Changes: 9-
• Added:
• - Specification Clarifications: 7-CLIST1 (D25:F0:Offset C8h-C9h) Register
• - Document Changes: 10-Device 31 Interrupt Pin Register Corrections,11-
• Added 82801IBM ICH9M and 82801IEM ICH9M-E specifications.
• Moved all Specification Changes, Specification Clarifications, and
• Added:
• Errata: 11-ICH9M LAN_PHY_PWR_CTRL Functionality
• Added:
• Specification Changes: 1-Clock Slew Rate Change
• Document Changes: 1-SATA Interlock Switch State (ISS) Bit Clarification,
- Errata 4, Intel ICH9 THRM Polarity on SMBus
- Errata 5, Intel ICH9 SPI_CS1# State
USB2.0 D+ and D- Maximum Driven Signal Level
Clarification
Support for USB Wake from S5
UHCI Run/Stop Bit Clarification
Connectivity Clarification, 3-External RTC Circuit Correction, 4-D31:F6:52h
Register Default Value Correction, 5-SPI_CS0# Description Correction, 6-
Miscellaneous Register Default Value Corrections
VSCC Clarifications
Clock Gating Control Register Clarification
Addition
Corrections, 8-EHCI Initialization Register 1 Clarification, 9-PCI Express*
Root Port Configuration Register Clarification
D31:F0 Capability List Pointer Addition
Documentation Changes to the parent doc (316972-003).
2-GPIO34 Power Well Correction, 3-Lan Device Initialization Register, 4-
HPET Timer.
ICH9 Level-Triggered Legacy IRQ
Miscellaneous Electrical Correction
GNT[3:0]# Pull up Enable Correction
Addition of EHCI Parity Error Response
Description
GLANCLK High Time/Low Time
BIOS VSCC and Management Engine
, 7-ICH9 High Speed (HS)
ICH9—Revision History
Specification Update
November 2007
February 2008
August 2007
March 2008
September
September
June 2007
June 2008
May 2008
July 2008
Date
2007
2008