NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 20

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

6.
7.
8.
20
3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not
Corrected EOIFD Bit Definition
Update the EOIFD bit definition in Section 20.1.45 of the Datasheet as follows:
Update GPIO Signals and Note #4 in Section 3.2 Output and I/O Signals
Planes and States
Make the following update to Section 3.2 Table 3-3 (UnMultiplexed GPIO Signals) and
Note #4 for Table 3-2 and Table 3-3 of the Datasheet
Table 3-3
2.22 General Purpose I/O Signals for more details on GPIO state after reset.
Correct Table 1-5 ICH9M-E Raid Support
Make the following correction to Section 1.3 Table 1-5 Intel of the Datasheet:
31:02
Signal Name
GPIO[28:27]
Bit
reset by CF9 reset (06h or 0Eh).
GPIO20
GPIO49
1
GPIO12
GPIO13
GPIO18
GPIO56
GPIO8
Reserved.
EOI Forwarding Disable (EOIFD) — R/W. When set, EOI messages are not claimed
on the backbone by this port and will not be forwarded across the PCIe link.
0 = Broadcast EOI messages that are sent on the backbone are claimed by this port
1 = Broadcast EOI messages are not claimed on the backbone by this port and will not
11
11
(Update for both Table 3-2 and Table 3-3)
and fowarded across the PCIe link.
be forwarded across the PCIe Link.
Power
Plane
Suspend
Suspend
Suspend
Suspend
Suspend
Core
Core
Core
During
Reset
Input
Input
Input
High
High
Low
Low
Low
UnMultiplexed GPIO Signals
Immediately
after Reset
See Note 2
Input
Input
Input
High
High
Low
Low
Description
with an exception to GPIO signals; refer to section
C3/
C4/
C5/C6
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
S1
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Documentation Changes
S3
Defined
Defined
Defined
Defined
Defined
Specification Update
Off
Off
Off
S4/S5
Defined
Defined
Defined
Defined
Defined
Off
Off
Off