FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 65

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

CR00
This register can only be accessed when the chip is in the Configuration Mode and after the CSR has
been initialized to 00H. The default value of this register after power up is 28H.
CR01
This register can only be accessed in the Configuration
initialized to 01H. The default value of this register after power up is 90H.
BIT NO.
BIT NO.
0,1,2,3
4, 6
0:1
5,6
2
3
5
7
4
7
Reserved
PDEN
FDC Power
Reserved
OSC
Valid
Reserved
Reserved
Reserved
Lock CRx
BIT NAME
BIT NAME
Read only. Read as 0
Power Down and Idle enable.
Read Only. A read returns a 0.
0 nDS1pin=nDS1, nMTR1pin=nMTR1
1 nDS1pin=Power Down, nMTR1pin=Idle
A high level on this bit, supplies power to the FDC (default). A low
level on this bit puts the FDC in low power mode.
Read only. A read returns bits 4 and 6 as a 0.
Oscillator Control.
0 = Oscillator OFF
1 = Oscillator ON (default)
A high level on this software controlled bit can be used to indicate
that a valid configuration cycle has occurred. The control software
must take care to set this bit at the appropriate times. Set to zero
after power up. This bit has no effect on any other hardware in the
chip.
Read Only. A read returns a 1.
Read Only. A read returns a 0.
A high level on this bit enables the reading and writing of CRxx
registers (Default). A low level on this bit disables the reading and
writing of all CRxx registers. Once set to 0, this bit can only be set
to 1 by a hard reset or power-up reset.
Table 34 - CR00
Table 35 - CR01
65
DESCRIPTION
DESCRIPTION
Mode
and
after the CSR has been