FDC37M707QFP Standard Microsystems (SMSC), FDC37M707QFP Datasheet - Page 150

• Manufacturer Part Number: FDC37M707QFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M707QFP

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

SMI Enable
Register 2
Default = 0x00
on Vcc POR
SMI Status
Register 1
Default = 0x00
on Vcc POR
SMI Status
Register 2
Default = 0x00
on Vcc POR
Default = 0x00
on VTR POR
NAME
0xB5 R/W
0xB6 R/W
0xB7 R/W
0xB8 R/W
INDEX
REG
This register is used to enable the different interrupt
sources onto the group nSMI output, and the group
nSMI output onto the nSMI frame in the Serial IRQ
stream.
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_P12: Enable 8042 P1.2 to route internally
Bit[5] Reserved
Bit[6] EN_SMI_S: Enables nSMI Interrupt onto
Bit[7] Reserved
This register is used to read the status of the SMI
inputs.
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT (Watch Dog Timer)
This register is used to read the status of the SMI
inputs.
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Bit[2] IRINT: This bit is set by a transition on the IR
Bit[3] Reserved
Bit[4] P12: 8042 P1.2. Cleared at source
Bit[7:5] Reserved
Bits[7:0] Reserved
pin (RDX2 or IRRX as selected in CR L5-F1-B6
i.e., after the MUX). Cleared by a read of this
register.
to nSMI. 0=Do not route to nSMI, 1=Enable
routing to nSMI.
Serial IRQ.
150
DEFINITION
STATE
C
C
C
C