NH82801IB S LA9M Intel, NH82801IB S LA9M Datasheet
NH82801IB S LA9M
Specifications of NH82801IB S LA9M
Related parts for NH82801IB S LA9M
NH82801IB S LA9M Summary of contents
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... ICH9DO, 82801IBM ICH9M, 82801IEM ICH9M-E, and ICH9M- SFF I/O Controller Hubs May 2010 ® Notice: The Intel I/O Controller Hub 9 (ICH9) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel Viiv, Intel vPro, Intel SingleDriver, Intel SpeedStep, Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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... Contents—ICH9 Contents Preface ...................................................................................................................... 6 Summary Tables of Changes...................................................................................... 7 Identification Information ....................................................................................... 10 Intel® ICH9 Device and Revision Identification ....................................................... 11 Errata ...................................................................................................................... 13 Specification Changes.............................................................................................. 18 Specification Clarifications ...................................................................................... 19 Documentation Changes .......................................................................................... 20 Specification Update 3 ...
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... Revision History Revision -001 • Initial Release • Added 82801IO ICH9DO specifications • Added following Errata -002 - Errata 4, Intel ICH9 THRM Polarity on SMBus - Errata 5, Intel ICH9 SPI_CS1# State • Added: • - Errata: 6- -003 USB2.0 D+ and D- Maximum Driven Signal Level • - Specification Clarifications: 1- Clarification • ...
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... Changes: 13-Correct PCI Express* DSTS register definition for bit 1 (NFED) Added items: - Errata: 12- Intel® I/O Controller Hub 9 (ICH9) Family SATA Low Power Device Detection -017 -Document Changes: 14 -Correct SMBCLK_CTL bit default value 15 - Correct Table 2-24 Strap selection for Boot BIOS Destination Added items: - Errata: 13- Intel® ...
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... This document may also contain information that was not previously published. Affected Documents/Related Documents ® Intel I/O Controller Hub 9 (ICH9) Family Datasheet Nomenclature Errata are design defects or errors. These may cause the Product Name’s behavior to deviate from published specifications ...
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... The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Product Name product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. ...
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... X No Fix Intel® I/O Controller Hub 9 (ICH9) Family X No Fix Intel® I/O Controller Hub 9 (ICH9) Family THRM Polarity on SMBus No Fix Intel® I/O Controller Hub 9 (ICH9) Family SPI_CS1# State Intel® I/O Controller Hub 9 (ICH9) Family Level-Triggered Legacy No Fix IRQ Intel® ...
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Summary Tables of Changes Documentation Changes (Sheet No. 4 HPET Timer 5 Add GPIO Signal Reset Notes 6 Corrected EOIFD bit definition 7 Update GPIO Signals and Note #4 in Section 3.2 Output and I/O Signals Planes ...
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... NH82801IB Intel 82801IB ICH9 ® NH82801IR Intel 82801IR ICH9R ® NH82801IH Intel 82801IH ICH9DH ® NH82801IO Intel 82801IO ICH9DO ® AF82801IBM Intel 82801IBM ICH9M ® AF82801IEM Intel 82801IEM ICH9M-E ® AM82801IUX Intel ICH9M-SFF § § Identification Information Notes Specification Update ...
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... Intel® ICH9 Device and Revision Identification ® Intel ICH9 Device and Revision Identification ICH9 Device and Revision ID Table Device Description Function LPC D31:F2 SATA D31:F5 SATA D31:F3 SMBus D31:F6 Thermal DMI to PCI D30:F0 Bridge Specification Update ® Intel ICH9 ICH9 ...
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... Refer to the ICH9 NVM Map and Programming Guide for LAN Device IDs. 3. The SATA RAID Controller Device ID may reflect a different value based on Bit 7 of D31:F2:Offset 9Ch. 12 Intel® ICH9 Device and Revision Identification ® Intel ICH9 ICH9 ICH9 ...
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... Errata Errata 1. Intel® I/O Controller Hub 9 (ICH9) Family UHCI Hang with USB Reset Problem: When SW initiates a Host Controller Reset or a USB Global Reset while concurrent traffic occurs on at least three UHCI controllers, the UHCI controller(s) may hang. Note: The issue has only been replicated in a synthetic reset test environment. ...
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... The receiver is pseudo differential design • The receiver is not able to ignore SE1 (single-ended) state Note: Intel has only observed this issue with a motherboard down HS USB 2.0 device using pseudo differential design. This issue will not affect HS USB 2.0 devices with complementary differential design or Low Speed (LS) and Full Speed (FS) devices Workaround: None ...
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... Problem: When using the ICH9 SMBus for Platform Event Trap (PET) alerts on a system with the Intel® Management Engine (ME) enabled, the SMBus packet headers may be corrupted if all of the following conditions are met: • SMBus slave is the target of an external PET generating master on SMBus/SMLink • ...
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... RTC clock cycles due to the pin momentarily being configured as an output GPIO. • LAN_PHY_PWR_CTRL functionality requires a soft strap setting in the SPI descriptor and use of the integrated LAN controller in ICH9M with the Intel® 82567 PHY. Implication: Functional failures such as system hangs or link loss with dropped packets have been observed when LAN_PHY_PWR_CTRL is tied to the LAN_DISABLE_N pin on the Intel® ...
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... Workaround: None Status: No Fix. For steppings affected, see the Summary Table of Changes. 15. Intel® I/O Controller Hub 9 (ICH9) Family HPET Write Timing Problem: A read transaction that immediately follows a write transaction to the HPET TIMn_COMP Timer 0 (108h), HPET MAIN_CNT (0F0h), or TIMn_CONF.bit 6 (100h) may ...
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Specification Changes 1. Clock Slew Rate Change The following change applies to Table 8-9 of the Datasheet. Sym SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN) tsatasl Slew rate 2. Serial ATA Clock Request Support. Serial ATA Clock Request ...
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Specification Clarifications Specification Clarifications 1. t290 and t294 Clarification a. Note 23 for t290 and t294 in Table 8-22 of the Datasheet is changed as indicated below: 23. t290 and t294 are not applied to V5REF. V5REF timings are bounded ...
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Documentation Changes 1. SATA Interlock Switch State (ISS) Bit Clarification The following change applies to Section 14.4.3.7 of the Datasheet. Interlock Switch State (ISS)— RO. For systems that support interlock switches (via CAP.SIS [ABAR+00h:bit28]), if an interlock switch exists on ...
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... GPIO20 Core GPIO[28:27] Suspend 11 GPIO49 Core GPIO56 Suspend 8. Correct Table 1-5 ICH9M-E Raid Support Make the following correction to Section 1.3 Table 1-5 Intel of the Datasheet: Specification Update Description with an exception to GPIO signals; refer to section C3/ During Immediately C4/ Reset after Reset C5/C6 UnMultiplexed GPIO Signals ...
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... ICH9M Yes ICH9M-E Yes Host Reset without Trigger No Description occurred. If this bit is set and the NO_REBOOT config bit is 0, then the Documentation Changes ® Intel Active Management Technology No No Yes Yes Host Reset Global with Power Reset with Power Cycle Power Cycle ...
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... GPIOs high. Some ICH9 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low Power Button Override event will result in the Intel ICH9 driving a pin to a logic 1 to another device that is powered down. ...
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When this signal is configured as GPO the output stage is an open drain. 13. Correct PCI Express* DSTS register definition for bit 1 (NFED) Update the bit definition for bit 1(NFED) in Section 20.1.27 DTST- Device Status Register ...
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Documentation Changes Signal Usage Boot BIOS GNT0# Destination Selection 1 SPI_CS1# / GPIO58 Boot BIOS Desktop Only) / Destination CLGPIO6 Selection 0 (Digital Office Only) 16. Correct section 5.13.7.5 Sx-G3-Sx, Handling Power Failures regarding possible wake events following a power ...
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The AFTER_G3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains state (unless previously in ...
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Documentation Changes Bit 31:24 Reserved Generic I/O Decode Range Address[7:2] Mask — R/ any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding ...