NH82801IB S LA9M Intel, NH82801IB S LA9M Datasheet - Page 24

• Manufacturer Part Number: NH82801IB S LA9M
• Manufacturer: Intel

Specifications of NH82801IB S LA9M

• Lead Free Status / RoHS Status: Compliant

13.
14.
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7.
Correct PCI Express* DSTS register definition for bit 1 (NFED)
Update the bit definition for bit 1(NFED) in Section 20.1.27 DTST- Device Status
Register Description in the Datasheet to match PCI Express* Base Specification
Revision 1.1.
Section 20.1.27 DSTS—Device Status Register
Address Offset: 4Ah–4Bh
Default Value:
Correct SMBCLK_CTL bit default value
Correct SMBCLK_CTL bit 2 default value defined in section 19.2.14
SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3) in the Datasheet
Correct Table 2-24 Strap selection for Boot BIOS Destination
Correct Boot BIOS Destination strap selection definition in Table 2-24 Functional Strap
Definitions (Sheet 2 of 3) in the Datasheet
Bit
Bit
2
1
When this signal is configured as GPO the output stage is an open drain.
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
0 = ICH9 drives the SMBCLK pin low, independent of what the other SMB logic would
Non-Fatal Error Detected (NFED) — R/WC. Indicates a non-fatal error was detected.
0 = Non-fatal has not occurred.
1 = A non-fatal error occurred.
the pin. (Default)
otherwise indicate for the SMBCLK pin.
0010h
Description
Description
Attribute:
Size:
R/WC, RO
16 bits
Documentation Changes
Specification Update