ISP1583ET2,518 NXP Semiconductors, ISP1583ET2,518 Datasheet - Page 97

• Manufacturer Part Number: ISP1583ET2,518
• Manufacturer: NXP Semiconductors

Specifications of ISP1583ET2,518

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 78. DMA Strobe Timing register: bit allocation . . .58
Table 79. DMA Strobe Timing register: bit description . .58
Table 80. DMA Burst Counter register: bit allocation . . .59
Table 81. DMA Burst Counter register: bit description . .59
Table 82. Interrupt register: bit allocation . . . . . . . . . . . .60
Table 83. Interrupt register: bit description . . . . . . . . . . .60
Table 84. Chip ID register: bit allocation . . . . . . . . . . . . .61
Table 85. Chip ID register: bit description . . . . . . . . . . . .62
Table 86. Frame Number register: bit allocation . . . . . . .62
Table 87. Frame Number register: bit description . . . . . .62
Table 88. Scratch register: bit allocation . . . . . . . . . . . . .62
Table 89. Scratch register: bit description . . . . . . . . . . . .63
Table 90. Unlock Device register: bit allocation . . . . . . . .63
Table 91. Unlock Device register: bit description . . . . . . .63
Table 92. Test Mode register: bit allocation . . . . . . . . . . .64
Table 93. Test Mode register: bit description . . . . . . . . . .64
Table 94. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 95. Recommended operating conditions . . . . . . . .65
Table 96. Static characteristics: supply pins . . . . . . . . . .65
Table 97. Static characteristics: digital pins . . . . . . . . . . .66
Table 98. Static characteristics: OTG detection . . . . . . .66
Table 99. Static characteristics: analog I/O pins
Table 100.Dynamic characteristics . . . . . . . . . . . . . . . . . .67
Table 101.Dynamic characteristics: analog I/O pins
Table 102.ISP1583 register access timing parameters:
Table 103.ISP1583 register access timing parameters:
Table 104.ISP1583 register access timing parameters:
Table 105.ISP1583 register access timing parameters:
Table 106.ISP1583 register access timing parameters:
Table 107.ISP1583 register access timing parameters:
Table 108.PIO mode timing parameters . . . . . . . . . . . . . .79
Table 109.GDMA slave mode timing parameters . . . . . . .81
Table 110.MDMA mode timing parameters . . . . . . . . . . .83
Table 111.SnPb eutectic process (from J-STD-020C) . . .90
Table 112.Lead-free process (from J-STD-020C) . . . . . .90
Table 113.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 114.Revision history . . . . . . . . . . . . . . . . . . . . . . . .93
ISP1583_7
Product data sheet
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .68
separate address and data buses . . . . . . . . . .69
separate address and data buses . . . . . . . . . .71
multiplexed address/data bus . . . . . . . . . . . . .73
multiplexed address/data bus . . . . . . . . . . . . .74
multiplexed address/data bus . . . . . . . . . . . . .75
multiplexed address/data bus . . . . . . . . . . . . .76
Rev. 07 — 22 September 2008
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
ISP1583
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