ISP1582BSUM STEricsson, ISP1582BSUM Datasheet - Page 10

• Manufacturer Part Number: ISP1582BSUM
• Manufacturer: STEricsson

Specifications of ISP1582BSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_9
Product data sheet
7.6.1 ST-Ericsson Parallel Interface Engine (PIE)
7.6.2 Peripheral circuit
7.6.3 HS detection
7.6.4 Isolation
7.6 ST-Ericsson high-speed transceiver
Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a
standard USB peripheral, can initiate SRP.
The ISP1582 is a device that can initiate SRP.
In the High-Speed (HS) transceiver, the ST-Ericsson PIE interface uses a 16-bit parallel
bidirectional data interface. The functions of the HS module also include bit-stuffing or
de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.
To maintain a constant current driver for HS transmit circuits and to bias other analog
circuits, an internal band gap reference circuit and an RREF resistor form the reference
current. This circuit requires an external precision resistor (12.0 kΩ ± 1 %) connected to
the analog ground.
The ISP1582 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS),
under the USB specification. When the USB cable is connected from the peripheral to the
host controller, the ISP1582 defaults to the FS state, until it sees a bus reset from the host
controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there
is an HS host connected, then the ISP1582 switches to the HS state.
In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains
inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero
(SE0) condition on the USB bus. If an SE0 condition is detected for the designated time
(100 μs to 875 μs; refer to
Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection
handshake. Otherwise, the ISP1582 remains in the FS state, adhering to the bus-suspend
specification.
Ensure that the DP and DM lines are maintained in a clean state, without any residual
voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that there
are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines.
Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1582
DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal
core, causing unknown behaviors.
Rev. 09 — 29 September 2009
Ref. 1 “Universal Serial Bus Specification Rev.
Hi-Speed USB peripheral controller
© ST-ERICSSON 2009. All rights reserved.
ISP1582
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