ISP1582BSUM STEricsson, ISP1582BSUM Datasheet - Page 33

• Manufacturer Part Number: ISP1582BSUM
• Manufacturer: STEricsson

Specifications of ISP1582BSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 35.
ISP1582_9
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Buffer Length register: bit allocation
8.3.5 Buffer Status register (address: 1Eh)
R/W
R/W
15
0
0
7
0
0
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer
Length register is not significant. This register is useful only when transferring data that is
not a multiple of MaxPacketSize. The following two examples demonstrate the
significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be filled. This is because
the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register must be filled with 62 bytes just
before the microprocessor writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use bit VENDP in the Control register if you are not using the Buffer Length register.
This is applicable only to the PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.
Table 36.
This register is accessed using index. The endpoint index must first be set before
accessing this register for the corresponding endpoint. It reflects the status of the double
buffered endpoint FIFO.
Remark: This register is not applicable to the control endpoint.
Bit
15 to 0
R/W
R/W
14
0
0
6
0
0
Symbol
DATACOUNT[15:0]
Buffer Length register: bit description
R/W
R/W
13
0
0
5
0
0
Rev. 09 — 29 September 2009
Description
Data Count: Determines the current packet size of the indexed
endpoint FIFO.
DATACOUNT[15:8]
R/W
DATACOUNT[7:0]
R/W
12
0
0
4
0
0
R/W
R/W
11
0
0
3
0
0
Hi-Speed USB peripheral controller
R/W
R/W
10
0
0
2
0
0
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
0
0
1
0
0
ISP1582
R/W
R/W
8
0
0
0
0
0
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