ISP1581BD STEricsson, ISP1581BD Datasheet - Page 33

• Manufacturer Part Number: ISP1581BD
• Manufacturer: STEricsson

Specifications of ISP1581BD

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 31:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Transfer Counter register: bit allocation
31
23
9.4.2 DMA Transfer Counter register (address: 34H)
Table 30:
[1]
This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR).
It indicates the remaining number of bytes left for transfer. The bit allocation is given
in
The transfer counter is used in DMA modes: PIO (commands: 04H, 05H), UDMA
(commands: 02H, 03H), MDMA (commands: 06H, 07H) and GDMA (commands:
00H, 01H).
A new value is written into the register starting with the lower byte (DMACR1) or the
lower word (MSByte: DMACR2, LSByte: DMACR1). Internally, the transfer counter is
initialized only after the last byte (DMACR4) has been written.
In the GDMA Slave mode only, the transfer counter can be disabled via bit
DIS_XFER_CNT in the DMA Configuration Register (see
input signal EOT can be used to terminate the DMA transfer when data is transferred
from the external device to the host via IN tokens. The last packet in the FIFO is
validated when pin EOT is asserted.
Code (Hex) Name
Table
13 to FF
PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.
30
22
11
12
31.
DMA commands
Reset DMA
MDMA stop
-
Rev. 06 — 23 December 2004
29
21
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
…continued
28
20
R/W
R/W
00H
00H
00H
00H
Description
Reset DMA: Initializes the DMA core to its power-on
reset state.
Remark: When the DMA core is reset during the Reset
DMA command, the DREQ, DACK, DIOW and DIOR
handshake pins will be temporarily asserted. This can
cause some confusion to the external DMA Controller.
To prevent this from happening, start the external DMA
Controller only after the DMA reset is done.
MDMA stop: This command immediately stops the
MDMA data transfer. This is applicable for commands
06H and 07H only.
reserved
27
19
Hi-Speed USB peripheral controller
26
18
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
33). In this case,
25
17
ISP1581
24
16
32 of 79